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preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use iii PM7341 s/uni-ima-84 s/uni inverse multiplexing for atm, 84 links datasheet proprietary and confidential preliminary issue 4: july 2001
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use iv revision history issue no. issue date details of change 1 february, 2000 creation of document. 2 march, 2000 added details in register section, functional description, operations and d.c. characteristics. 3 february, 2001 added details in interrupt reporting structure, sbi async/sync support clarified. increased number of tadr pins to 11 for glueless interconnect to the s/uni- apex. rearranged ima context and configuration tables. added capability to add/delete delay from active groups. 4 july, 2001 additional detailed added.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use v contents 1 definitions ........................................................................................ 23 2 features ............................................................................................ 25 3 applications ..................................................................................... 31 4 references....................................................................................... 32 5 application examples ................................................................... 33 5.1 atm multiservice switch ima / uni port card............. 33 5.2 atm multiservice switch, any service any port card .................................................................................................... 33 6 block diagram ................................................................................. 35 7 description....................................................................................... 36 8 pin diagram ....................................................................................... 39 9 pin description................................................................................ 41 9.1 receive slave atm interface (any-phy mode) (28 signals).................................................................................... 41 9.2 receive slave atm interface (utopia l2 mode) (26 signals).................................................................................... 44 9.3 transmit slave interface (any-phy mode) (34 signals)46 9.4 transmit slave interface (utopia l2 mode) (26 signals).................................................................................... 49 9.5 microprocessor interface (31 signals)..................... 51 9.6 sdram i/f (35 signals) .......................................................... 53 9.7 clk/data (129 signals).......................................................... 56 9.8 sbi interface signals (27).................................................. 60
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use vi 9.9 general (5 signals) ............................................................. 65 9.10 jtag & scan interface (7 signals) .................................. 67 9.11 power (120 signals) ............................................................. 68 10 functional description............................................................... 71 10.1 any-phy/utopia interfaces ............................................... 71 10.1.1 transmit any-phy/utopia slave (txaps).............. 72 10.1.2 receive any-phy/utopia slave (rxaps)................ 75 10.1.3 summary of any-phy/utopia modes ..................... 79 10.1.4 any-phy/utopia loopback ....................................... 81 10.2 ima sub-layer ......................................................................... 81 10.2.1 overview ...................................................................... 81 10.2.2 idcc scheduler.......................................................... 82 10.2.3 transmit ima processor (tima) ............................ 83 10.2.4 receive ima data processor (rdat) .................... 87 10.2.5 receive ima protocol processor (ripp) ........ 100 10.2.6 support of ima test pattern procedure ....... 111 10.2.7 support of symmetric/asymmetric operation modes ........................................................................... 111 10.2.8 support of different ima versions.................. 111 10.2.9 sdram interface.......................................................112 10.3 link fifos................................................................................115 10.4 tc layer ..................................................................................115 10.4.1 tx tc layer (tttc) .....................................................115
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use vii 10.4.2 rx tc layer (rttc).....................................................116 10.5 line side physical layer ...................................................118 10.5.1 tx clock/data (tcas) ................................................118 10.5.2 tx null framer (sdfr84).........................................119 10.5.3 insert scaleable bandwidth interconnect (insbi).............................................................................119 10.5.4 extract scaleable bandwidth interconnect (exsbi)............................................................................119 10.5.5 rx deframer (sddf84) ............................................ 120 10.5.6 rx clock/data (rcas) .............................................. 120 10.6 microprocessor interface .......................................... 121 10.6.1 mapping and link identification......................... 121 10.6.2 interrupt driven error/status reporting .. 123 10.6.3 registers................................................................... 124 11 normal mode register description ..................................... 131 11.1 global registers .............................................................. 132 11.2 master interrupt registers ........................................ 137 11.3 utopia interface registers .......................................... 147 11.4 sdram registers................................................................ 156 11.5 tc layer registers ........................................................... 166 11.6 sbi registers....................................................................... 177 11.7 line clock/data interface .............................................. 203 11.8 ripp registers .................................................................... 217
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use viii 11.9 rdat registers ................................................................... 292 11.10 tima registers .................................................................... 325 11.11 tx idcc registers .............................................................. 341 11.12 rx idcc registers .............................................................. 347 12 operation ........................................................................................ 351 12.1 hardware configuration............................................... 351 12.2 start-up ................................................................................. 351 12.3 configuring the s/uni-ima-84.......................................... 352 12.3.1 configuring sbi interface .................................. 352 12.3.2 configuring clock/data interface .................. 354 12.3.3 configuring tc layer options ........................... 356 12.3.4 utopia interface configuration....................... 357 12.4 ima_layer configuration................................................ 358 12.4.1 indirect access to internal memory tables 358 12.4.2 configuring links for transmission convergence operations ................................... 359 12.4.3 configuring for ima operations ...................... 361 12.5 ima operations .................................................................... 365 12.5.1 issuing a ripp command......................................... 365 12.5.2 summary of ripp commands ................................ 366 12.5.3 adding a group......................................................... 371 12.5.4 deleting a group..................................................... 372 12.5.5 restart group ......................................................... 372
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use ix 12.5.6 inhibit group/not inhibit group......................... 373 12.5.7 adding a link or links to an existing group (start lasr) ............................................................... 373 12.5.8 reporting link defects in the icp cell .......... 374 12.5.9 faulting/inhibiting links ...................................... 374 12.5.10 change trl............................................................ 374 12.5.11 deleting a link from a group......................... 375 12.5.12 test pattern procedures .............................. 375 12.5.13 ima events ............................................................. 375 12.5.14 end-to-end channel communication........... 376 12.6 diagnostic features ........................................................ 376 12.6.1 icp cell trace........................................................... 376 12.6.2 sdram diagnostic access .................................... 377 12.7 ima performance parameters and failure alarms support ................................................................................. 378 13 functional timing......................................................................... 382 13.1 sbi drop bus interface timing ...................................... 382 13.2 sbi add bus interface timing ......................................... 383 13.3 receive link input timing................................................. 384 13.4 transmit link output timing .......................................... 385 13.5 any-phy/utopia l2 interfaces ........................................ 388 13.5.1 utopia l2 transmit slave interface ................. 388 13.5.2 any-phy transmit slave interface.................... 389
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use x 13.5.3 utopia l2 multi-phy receive slave interface 390 13.5.4 utopia l2 single-phy receive slave interface 391 13.5.5 any-phy receive slave interface ...................... 392 13.6 sdram interface ................................................................ 392 14 absolute maximum ratings ....................................................... 397 15 d. c. characteristics .................................................................. 398 16 a.c. timing characteristics...................................................... 401 16.1 microprocessor interface timing characteristics .................................................................................................. 401 16.2 synchronous i/o timing................................................... 405 16.3 sbi timing ............................................................................... 409 16.4 jtag timing ............................................................................ 412 17 ordering and thermal information...................................... 414 18 mechanical information ............................................................ 415
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use xi list of figures figure 1 - atm edge switch ima and uni port card example ..... 33 figure 2 - atm multiservice switch, any service any port card example 34 figure 3 - s/uni-ima-84 block diagram................................................ 35 figure 4 - s/uni-ima pinout (bottom view)......................................... 40 figure 5 - 16-bit transmit cell transfer format ......................... 74 figure 6 - 8-bit transmit cell transfer format ........................... 74 figure 7 - 16-bit receive cell transfer format............................ 78 figure 8 - 8-bit receive cell transfer format.............................. 78 figure 9 - inverse multiplexing .......................................................... 82 figure 10- max differential delay tolerance vs. sdram size .. 88 figure 11 - ifsm state machine............................................................... 89 figure 12- stuff event with errored icp (advanced indication) 91 figure 13- invalid stuff sequence (advanced indication) ......... 91 figure 14- errored/invalid icp cells in proximity to a stuff event 92 figure 15- snapshot of dcb buffers ................................................. 93 figure 16- snapshot of dcb buffers after addition of link with smaller transport delay...................................................................... 94 figure 17- snapshot of dcb buffers when trying to add link with larger transport delay.............................................................. 95 figure 18- snapshot of dcb buffers after delay adjustment 96
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use xii figure 19- snapshot of dcb buffers after deletion of links from group 97 figure 20- ima error/maintenance state diagram ........................ 98 figure 21- cell storage map................................................................112 figure 22- 2 mbyte ....................................................................................113 figure 23- 8 mbyte ....................................................................................114 figure 24- cell delineation state diagram.....................................117 figure 25-burst ram format ............................................................... 161 figure 26- sbi drop bus t1/e1 functional timing.......................... 382 figure 27- sbi drop bus ds3 functional timing ............................ 382 figure 28- sbi add bus adjustment request functional timing 383 figure 29- unchannelized receive link timing ............................. 384 figure 30- channelized t1 receive link timing ............................. 385 figure 31- channelized e1 receive link timing ............................. 385 figure 32- unchannelized transmit link timing........................... 386 figure 33- channelized t1 transmit link timing w/ clock gapped low 386 figure 34- channelized t1 transmit link timing w/ clock gapped high 387 figure 35- channelized e1 transmit link timing w/ clock gapped low 387 figure 36- channelized e1 transmit link timing w/ clock gapped high 387 figure 37- utopia l2 transmit slave ................................................. 389
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use xiii figure 38- any-phy transmit slave .................................................... 390 figure 39- utopia l2 multi-phy receive slave ................................ 391 figure 40- utopia l2 single-phy receive slave ............................. 391 figure 41- any-phy receive slave ...................................................... 392 figure 42- sdram read timing ............................................................. 393 figure 43- sdram write timing ............................................................ 394 figure 44- sdram refresh.................................................................... 395 figure 45- power up and initialization sequence ....................... 396 figure 46- microprocessor interface read timing................... 402 figure 47- microprocessor interface write timing ................. 404 figure 48- rstb timing............................................................................ 405 figure 49- synchronous i/o timing ................................................... 405 figure 50- sbi frame pulse timing ..................................................... 409 figure 51- sbi drop bus timing ............................................................ 410 figure 52- sbi add bus timing................................................................411 figure 53- sbi add bus collision avoidance timing ......................411 figure 54- jtag port interface timing............................................. 413 figure 55- 416 pin pbga ?27x27 mm body ? (p suffix) ..................... 415
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use xiv list of tables table 1 terminology............................................................................. 23 table 2 utopia l2 and any-phy comparison ................................... 76 table 3 pm command description .................................................. 101 table 4 register memory map ......................................................... 125 table 5 configuration memory address space ....................... 218 table 6 context memory address space .................................... 219 table 7 ripp group configuration record structure ........ 221 table 8 rx physical link table ........................................................ 229 table 9 ripp tx link configuration record structure ........ 230 table 10 ripp rx link configuration record structure........ 232 table 11 ripp group context record structure ..................... 234 table 12 ripp tx link context record structure..................... 249 table 13 ripp rx link context record structure .................... 253 table 14 command register encoding........................................... 271 table 15 command data register array format ........................ 282 table 16 group error/status bit mapping ................................... 284 table 17 link event interrupt bit mapping................................... 286 table 18 link status bit mapping ...................................................... 288 table 19 receive icp cell buffer structure .............................. 290 table 20 rdat link statistics record (ima) ................................... 297 table 21 rdat link statistics record (tc)..................................... 298
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use xv table 22 rdat ima group statistics record................................. 299 table 23 rdat tc link statistics record ....................................... 300 table 24 rdat validation record ..................................................... 301 table 25 rdat link context record ................................................ 304 table 26 rdat link message status record................................. 309 table 27 receive icp cell buffer structure .............................. 310 table 28 rdat ima group context record.................................... 312 table 29 rdat tc link context record .......................................... 314 table 30 receive atm congestion count register ................... 315 table 31 transmit ima group context record ........................... 330 table 32 transmit ima group configuration table record .... 333 table 33 transmit lid to physical link mapping table ............. 335 table 34 tima physical link context record............................... 336 table 35 refclk/sysclk frequency requirement ..................... 356 table 36 ima performance parameter support......................... 378 table 37 ima failure alarm support................................................ 379 table 38 absolute maximum ratings ............................................... 397 table 39 d.c. characteristics ........................................................... 398 table 40 microprocessor interface read access................... 401 table 41 microprocessor interface write access ................. 403 table 42 rtsb timing .............................................................................. 404 table 43 sysclk and refclk timing .................................................. 405
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use xvi table 44 cell buffer sdram interface .......................................... 406 table 45 any-phy/utopia transmit interface ............................... 406 table 46 any-phy/utopia receive interface.................................. 407 table 47 serial link input.................................................................... 407 table 48 serial link output................................................................ 408 table 49 sbi frame pulse timing ....................................................... 409 table 50 sbi drop bus timing .............................................................. 409 table 51 sbi add bus .............................................................................. 410 table 52 jtag port interface ............................................................ 412 table 53 ordering and thermal information.............................. 414 table 54 thermal information - theta ja vs. airflow ............... 414
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use xvii list of registers register 0x000: global reset ............................................................. 132 register 0x002: global configuration ........................................... 133 register 0x004: jtag id (msb)................................................................ 135 register 0x006: jtag id (lsb)................................................................. 136 register 0x008: master interrupt register................................. 137 register 0x00a: miscellaneous interrupt register................. 140 register 0x00c: receive tc interrupt fifo.................................... 142 register 0x010: master interrupt enable register ................. 144 register 0x012: miscellaneous interrupt enable register .. 145 register 0x014: tc interrupt enable register............................ 146 register 0x020: transmit any-phy/utopia cell available enable 147 register 0x022: receive utopia cell available enable .............. 148 register 0x024: receive any-phy/utopia config reg (rxaps_cfg) 149 register 0x026: transmit any-phy/utopia config reg (txaps_cfg)151 register 0x028: transmit any-phy address config register (txaps_add_cfg) ...................................................................................... 153 register 0x040: sdram configuration ............................................ 156 register 0x042 sdram diagnostics................................................... 157 register 0x044: sdram diag burst ram indirect access .......... 158 register 0x046: sdram diag indirect burst ram data lsb ........ 159
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use xviii register 0x048: sdram diag indirect burst ram data msb ....... 160 register 0x04a: sdram diag write cmd 1 ........................................ 162 register 0x04c: sdram diag write cmd 2 ........................................ 163 register 0x04e: sdram diag read cmd 1 .......................................... 164 register 0x050: sdram diag read cmd 2 .......................................... 165 register 0x060: tttc indirect link control register............... 166 register 0x062: tttc indirect link configuration register .. 168 register 0x070: rttc indirect link control register .............. 169 register 0x072: rttc indirect link configuration register .. 171 register 0x074: rttc indirect link interrupt and status register 173 register 0x076: rttc indirect link hcs error count register 175 register 0x078: lcd count threshold ............................................ 176 register 0x080: sbi bus configuration register (sbi_bus_cfg_reg) ................................................................................... 177 register 0x084-0x08e: sbi extract alarm interrupt register 179 register 0x090-0x09a: sbi extract alarm status register...... 180 register 0x0a0: sbi extract control register........................... 181 register 0x0a2: sbi extract fifo underrun interrupt register 183 register 0x0a4: sbi extract fifo overrun interrupt register 184 register 0x0a6: sbi extract tributary control ram indirect access address register.................................................................... 185
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use xix register 0x0a8: sbi extract tributary control ram indirect access control register ................................................................... 186 register 0x0ac: sbi extract tributary control ram indirect access data register ............................................................................ 187 register 0x0ae: sbi extract parity error interrupt register 188 register 0x0bc: sbi extract depth check interrupt register 189 register 0x0be: sbi extract master interrupt register ....... 190 register 0x0c0: sbi insert control register .............................. 192 register 0x0c2: sbi insert fifo underrun interrupt register 194 register 0x0c4: sbi insert fifo overrun interrupt register 195 register 0x0c6: sbi insert tributary control ram indirect access address register.................................................................... 196 register 0x0c8: sbi insert tributary control ram indirect access control register ................................................................... 197 register 0x0cc: sbi insert tributary control ram indirect access data register ............................................................................ 198 register 0x0e2: sbi insert depth check interrupt register. 200 register 0x0e4: sbi insert master interrupt register ........... 201 register 0x100: rcas indirect link and time-slot control register 203 register 0x102: rcas indirect link data register ...................... 205 register 0x104: rcas framing bit threshold ............................... 207 register 0x106: rcas link disable ..................................................... 208 register 0x140- 0x17e: rcas link #0 to link #31 configuration209
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use xx register 0x180: tcas indirect link and time-slot control register 210 register 0x182: tcas indirect link data register....................... 212 register 0x184: tcas framing bit threshold................................ 213 register 0x186: tcas idle time-slot fill data................................ 214 register 0x188: tcas link disable register .................................. 215 register 0x1c0 ? 0x1fe: tcas link #0 to link #31 configuration 216 register 0x200:ripp control .............................................................. 217 register 0x202:ripp indirect memory access control ............ 218 register 0x204 ? 0x206:ripp indirect memory data register array 220 register 0x20c: ripp timer tick configuration register ........ 261 register 0x20e: group timeout register #1 ................................. 262 register 0x210: group timeout register #2 .................................. 263 register 0x212: tx link timeout register ...................................... 264 register 0x214: rx link timeout register ...................................... 265 register 0x216: ripp interrupt fifo ................................................. 266 register 0x218:ripp group interrupt enable register ........... 267 register 0x21a:ripp tx link interrupt enable register .......... 268 register 0x21c:ripp rx link interrupt enable register.......... 269 register 0x220-22c: ripp command register ................................. 270 register 0x22e: command read data control register........... 276 register 0x230: icp cell forwarding status register ............. 277
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use xxi register 0x232: icp cell forwarding control register ......... 278 register 0x240- 0x2be:ripp command data register array...... 279 register 0x2c0- 0x2fe: forwarding icp cell buffer.................. 289 register 0x300: rdat indirect memory command ........................ 292 register 0x302: rdat indirect memory address .......................... 294 register 0x304: rdat indirect memory data lsb .......................... 295 register 0x306: rdat indirect memory data msb ......................... 296 register 0x308: rdat configuration ................................................ 316 register 0x30a: receive atm congestion interrupt lsb.......... 318 register 0x30c: receive atm congestion interrupt msb......... 319 register 0x30e: receive tc link fifo overrun interrupt register 320 register 0x310: rdat master interrupt register ...................... 321 register 0x312: receive atm congestion interrupt enable lsb 322 register 0x314: receive atm congestion interrupt enable msb 323 register 0x316: rdat master interrupt enable .......................... 324 register 0x320: tima indirect memory command ......................... 325 register 0x322: tima indirect memory address ........................... 327 register 0x324: tima indirect memory data lsb............................ 328 register 0x326: tima indirect memory data msb........................... 329 register 0x328-0x332 transmit link fifo overrun interrupt register 339
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use xxii register 0x336 interrupt enable...................................................... 340 register 0x340: txidcc indirect link control register........... 341 register 0x342: txidcc indirect link data register ................... 343 register 0x350: rxidcc indirect link control register .......... 347 register 0x352: rxidcc indirect link data register................... 349 register 0x366: dll status register................................................ 350
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 23 1 definitions table 1 terminology term definition any-phy interoperable version of utopia and utopia l2, with inband addressing. atm asynchronous transfer mode cdv cell delay variation ctc common transmit clock dll delay locked loop ecbi enhanced common bus interface (asynchronous register bus and interface) exsbi extract scalable bandwidth interconnect fifo first-in-first-out framed framing information available ? may be channelized or unchannelized. hec header error check hcs header check sequence icp ima control protocol cell idcc ima data cell clock idcr ima data cell rate ifsn ima frame sequence number ima inverse multiplexing for atm insbi insert scalable bandwidth interconnect itc independent transmit clock lcd loss of cell delineation lid link id lsi link stuff indication mib management information base
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 24 mcfd multi-channel cell based fifo oam operation, administration and maintenance ocd out of cell delineation piso parallel in serial out pm plane management (microprocessor) rcas receive channel assigner rdat rx ima data processor ripp rx ima protocol processor rmts rx master tx slave sbi scalable bandwidth interconnect sipo serial in parallel out spe synchronous payload envelope tc transmission convergence tcas transmit channel assigner tdm time division multiplexing trl timing reference link trlcr trl cell rate tsb telecom systems block tc transmission convergence tima tx ima processor unframed no framing information available utopia universal test & operations phy interface for atm
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 25 2 features the PM7341 s/uni-ima-84 is a monolithic integrated circuit that implements the atm forum inverse multiplexing for atm (ima 1.1) protocol with backward compatibility to ima 1.0 and the transmission convergence (tc) layer function. the s/uni-ima-84 has two line side interface modes that determine the total number of physical links supported: the scalable bandwidth interconnect (sbi) bus interface mode and the clock and data interface mode. in sbi mode, the s/uni-ima-84 supports up to 84 t1, 63 e1 or 3 ds3 (tc only) physical links where each link is dynamically configurable to support either ima 1.1, backward compatible ima 1.0, atm over t1/e1 or up to three atm over ds3 streams (using hec delineation). in clock and data mode, the s/uni-ima-84 supports 32 independent t1, e1 or unchannelized physical links. each link is dynamically configurable to support either ima 1.1, backward compatible ima 1.0, or atm hec cell delineation. atm over fractional t1/e1 is also supported. unchannelized links may be used to support applications such as g.shdsl. standards supported ? atm forum inverse multiplexing for atm specification version 1.1, march 1999 ? atm forum inverse multiplexing for atm specification version 1.0 ? supports the method of reporting rx cell information as in appendix c.8 of the atm forum inverse multiplexing for atm specification version 1.1 for symmetrical configurations with m=128. ? i.432-1 b-isdn user network interface ? physical layer specification: general characteristics ? i.432-3 b-isdn user network interface ? physical layer specification: 1544 kbps and 2048 kbps operation ? ds3 physical layer interface specification, af-phy-0054.000 january, 1996 ? atm on fractional e1/t1, af-phy-0130.00 october, 1999.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 26 ima features ? ima 1.1 protocol including group and link state machines implemented by on- chip hardware. ? all icp cell processing is performed internally by the s/uni-ima device with no requirement for microprocessor intervention; however, icp cells are made available for diagnostic purposes. ? supports up to 42 simultaneous ima groups. ? each ima group can support 1 to 32 links chosen from any of the supported links. ? each link can be programmed for either ima processing or cell delineation. ? supports all ima group symmetry modes: ? symmetrical configuration with symmetrical operation ? symmetrical configuration with asymmetrical operation. ? asymmetrical configuration with asymmetrical operation. ? performs ima differential delay calculation and synchronization. ? provides programmable limit on allowable differential delay and minimum number of links per group. ? supports up to 279 ms (for t1 links) and 226 ms (for e1 links) link-differential delay among links in an ima group. ? performs icp and stuff-cell insertion and removal. ? supports both common transmit clock (ctc) and independent transmit clock (itc) transmit icp stuffing modes. ? supports ima frame lengths (m) equal to 32, 64, 128, or 256. ? optionally supports the ima 1.0 method of reporting rx cell information as defined in appendix c.8 of the atm forum inverse multiplexing for atm specification version 1.1 for symmetrical configurations with m=128.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 27 ? provides ima layer statistic counts and alarms for support of ima performance and failure alarm monitoring and mib support. ? provides per link counters for statistics and performance monitoring: ? icp violations ? oif anomalies ? rx link stuff events ? tx link stuff events ? user cells ? filler cells ? provides per group counters for statistics and performance monitoring: ? user cells received ? filler cells received ? user cells transmitted ? filler cells transmitted tc features ? performs cell delineation on all links. ? performs receive cell header error check (hec) checking and transmit cell hec generation. ? optionally supports receive cell payload unscrambling and transmit cell payload scrambling. ? provides tc layer statistics counts and alarms for mib support.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 28 interface support ? two line side interface modes: scalable bandwidth interconnect (sbi) bus and clock and data. sbi interface: ? supports a byte serial 19.44 mhz scalable bandwidth interconnect (sbi) bus interface for high-density line-side device interconnection of up to 84 t1, 63 e1, or three ds3 streams. ? the sbi interface bus uses three synchronous payload envelopes (spe) where each spe can carry up to 28 framed t1, 21 framed e1, or one framed ds3 stream. ? for spes configured to support ds3, tc layer processing is supported only. ima is not supported over ds3. ? always acts as a clock slave receiving clock rate information from the sbi based framer. ? supports common transmit clock (ctc) and independent transmit clock (itc) modes across the sbi bus. ? seamlessly interconnects to pmc-sierra?s pm8315 temux and pm8316 temux-84 highly integrated t1/ e1 framers, m13 muxs and sonet/sdh vt/tu mapper devices clock/data interface: ? supports 32 individual serial (t1 or e1 or unchannelized rates up to 2.304 mbps) links or 8 individual serial 8mbps unchannelized links via a 2-pin clock and data interface. ? supports atm over fractional t1/e1 by providing the capability to select any ds0 timeslots that are active in a link. ? serial link interface supports both independent transmit clock (itc) and common transmit clock (ctc) options.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 29 ? interfaces to a 1m x 16 ( for at least 69 msec of t1, 56 msec of e1 differential delay tolerance)or 4m x 16 sdram ( for 279 msec of t1, 226 msec of e1 differential delay tolerance) through a 16-bit sdram interface. ? provides a 16-bit microprocessor bus interface for configuration and link and unit management. ? atm receive interface supports 8- and 16-bit utopia l2 or any-phy cell interfaces at clock rates up to 52 mhz. ? any-phy receive slave appears as single device. the phy-id of each cell is identified in the in-band address. ? utopia l2 receive slave appears as a 31 port multi-phy. ? utopia l2 receive slave can also appear as a single port with the logical port provided as a prepend or in the hec/udf field. ? atm transmit interface supports 8- and 16-bit utopia l2 and any-phy cell interfaces at clock rates up to 52 mhz. ? each link configured for cell delineation or each ima group appears as a phy port on the any-phy and utopia l2 bus. ? any-phy transmit slave appears as an 84-port multi-phy. the phy-id of each cell is identified in the in-band address. ? utopia l2 transmit slave appears as a 31-port multi-phy. ? seamlessly interconnects to pmc-sierra?s pm7326 s/uni-apex atm/packet traffic manager and switch and pm7324 s/uni-atlas atm layer devices. loopback and diagnostic features ? supports utopia l2 / any-phy loopback (global loopback? where all cells received on the utopia l2 / any-phy interface are looped back out) ? supports line side loopback (global loopback? where all data received on the line side is looped back out) ? supports the capability to trace icp cells for any group
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 30 software ? the s/uni-ima device driver, written in ansi c, provides a well-defined application programming interface (api) for use by application software. low level utility functions are also provided for diagnostics and debugging purposes. software wrappers are used for rtos-related functions making the s/uni-ima device driver portable to any real time operating system (rtos) and hardware environment. the s/uni-ima device driver is compatible across the s/uni-ima family of devices. packaging ? implemented in low power, 0.18 micron, 1.8v cmos technology with ttl compatible inputs and outputs. ? provides a standard 5-pin p1149 jtag port.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 31 3 applications the s/uni-ima-84 is ideal for the following applications: ? atm multiservice switches - ima/uni and any service any port linecards ? wireless base station controllers
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 32 4 references ? af-phy-0086.001 ?inverse multiplexing for atm (ima) specification version 1.1?, march 1999 ? i.432-1 b-isdn user network interface ? physical layer specification: general characteristics ? i.432-3 b-isdn user network interface ? physical layer specification: 1544 kbps and 2048 kbps operation ? g.804 ?atm cell mapping into plesiochronous digital hierarchy (pdh)? ? af-phy-0016.000 ?atm forum ds1 physical layer specification? ? af-phy-0064.000 ?atm forum e1 physical interface? ? atm forum, utopia, an atm-phy layer specification, level 2, v. 1.0, foster city, ca usa, june 1995.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 33 5 application examples 5.1 atm multiservice switch ima / uni port card an optimized solution comprising the s/uni-ima-84, pm8316 temux-84, pm5342 spectra-155, pm7326 s/uni-apex, pm7324 s/uni-atlas devices enables a new generation of high density port cards for terminating n x ds3, n x oc-3?s worth of ima and/or atm uni circuits. see figure 1. figure 1 - atm edge switch ima and uni port card example utopia l2 / any-phy sbi telecom bus PM7341 s/uni-ima-84 pm8316 temux-84 pm7326 s/uni-apex pm7324 s/uni-atlas pm5342 spectra-155 pm5342 spectra-155 ds3 lius or pm5342 spectra-155 with a pm5313 spectra-622, four temux-84s, four s/uni-ima-84s, pm7326 s/uni-apex, and pm7324 s/uni-atlas devices, an oc-12?s worth of ima/uni circuits can be terminated on a single linecard. 5.2 atm multiservice switch, any service any port card with the s/uni-ima-84 and its support for the sbi tm bus, high density any service any port linecards for atm switches can be designed with pmc-sierra?s spectra tm , temux tm , aal1gator tm , s/uni -ima, freedm tm , s/uni - apex tm and s/uni -atlas tm products for supporting a broad spectrum of existing and emerging services including frame relay (fr), multi-link frame relay, multi-link ppp, internet protocol (ip), dedicated private line, integrated voice and data, voice-over- ip and voice-over-atm as shown in figure 2.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 34 figure 2 - atm multiservice switch, any service any port card example oc-12 sts-12 sonet/sdh framer telecom t1/j1/e1 framer tu/vt mapper m13 mux sbi packet processor aal1 circuit emulation service voice processor any-phy utopia l2 / any-phy oam and policing traffic manager h-mvip pm5313 spectra- 622 rm7000 mips processor dsp pm73122 aal1gator-32 PM7341 s/uni-ima-84 pm7389 freedm-84 packet/cell internetworking function appi utopia pm7324 s/uni-atlas pm7326 s/uni-apex voatm voice processing circuit emulation service ml-ppp and ml-frame relay ima / uni pm8316 temux-84 pm8316 temux-84 pm8316 temux-84 pm8316 temux-84 ima / uni the s/uni-ima-84 implements the ima 1.1 protocol (with backward compatibility to ima 1.0) including link and group state machines, hec cell delineation (uni), cell scheduling and provides internal cell fifos. the s/uni-ima-84 interfaces seamlessly over a standard utopia level 2 or any-phy bus to an atm traffic management device such as the pm7326 s/uni-apex. depending on the s/uni-ima-84?s register configuration, atm traffic is sent over the network as part of an ima 1.1 or ima 1.0 group or over a standard atm over t1/e1 or ds3 uni. through register programming, for example, the number of links, groups, minimum and maximum number of links/group, frame sizes (m=32, 64, 128, 256), differential delay tolerance, transmit clock mode (independent and common) and symmetrical/asymmetrical configuration and operation are dynamically configurable. an external low-cost standard 4mx16 sdram is required to buffer data for tolerating up to a maximum of 279 msec (t1) / 226 msec (e1) of differential delay across the links.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 35 6 block diagram figure 3 - s/uni-ima-84 block diagram tc layer (rttc84) insbi exsbi de- framer (sddf84) tc layer (tttc84) rx ima protocol processor (ripp) idcc 84-chan x 7 cell fifo (mcfd) 84-chan x 3 cell fifo tx ima processor (tima) any-phy/ utopia tx slave (txaps) any-phy/ utopia rx slave (rxaps) 31 chan 4 cell fifo microprocessor i/f jtag idcc dll 84-chan x 2 cell fifo null framer (sdfr84) tx slave atm i/f rx slave atm i/f sbi drop bus i/f 32 clk/data rcas tcas internal bus rx ima data processor (rdat) cell writer cell reader memory interface (memi) cbcsb cbrasb cbcasb cbweb cba[11:0] cbbs[1:0] cbdqm cbdq[15:0] rclk radr[4:0] renb rpa rcsb rsop rsx rdat[15:0] rprty tclk tadr[10:0] tenb tpa tcsb tsop tsx tdat[15:0] tprty d[15:0] a[10:1] ale wrb rdb csb intb tck tms tdi trstb tdo sysclk rstb oe dc1fp dpl ddp ddata[7:0] dv5 ac1fp adata[7:0] adp apl av5 ajust_req aactive adetect sbi add bus i/f tsclk[31:0] tsdata[31:0] 32 clk/data rsclk[31:0] rsdata[31:0] ctsclk refclk u2u_loop vl.dlb.en line_loop
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 36 7 description the PM7341 s/uni-ima-84 is a monolithic integrated circuit that implements the inverse multiplexing for atm (ima 1.1) protocol with backward compatibility to ima 1.0 and the transmission convergence (tc) layer function. the s/uni- ima-84 has two line side interface modes that determine the total number of links supported: the scalable bandwidth interconnect (sbi) bus interface mode and the clock and data interface mode. in sbi mode, the s/uni-ima-84 supports up to 84 t1, 63 e1 and 3 ds3 (tc only) links where each link is dynamically configurable to support either ima 1.1, backward compatible ima 1.0, atm over t1/e1 and up to three atm over ds3 streams (using hec delineation). in the clock and data interface mode, the s/uni-ima-84 supports 32 independent t1, e1 or unchannelized links. each link is dynamically configurable to support either ima 1.1, backward compatible ima 1.0, or atm hec cell delineation. atm over fractional t1/e1 is also supported. unchannelized links may be used to support applications such as g.shdsl. all links within an ima group must be the same nominal rate, however the link rates within a group can be different across groups. the scaleable bandwidth interconnect (sbi) high-density byte serial system interface provides higher levels of integration and dense interconnect. the sbi bus interconnects up to 84 t1s or 63 e1s asynchronously. the sbi allows transmit timing to be mastered by the phy layer device connected to the sbi bus with the s/uni-ima-84 always behaving as a clock slave. in addition to framed t1s and e1s, the s/uni-ima-84 can transport framed ds3 links over the sbi bus. the s/uni-ima-84 also supports a clock and data interface mode where 32 2-pin serial clock and data interfaces are provided. each clock and data interface can be configured to support either a t1 link, e1 link, or an unchannelized link. for ima, all links within a group must be the same nominal rate, but ima groups consisting of either e1 or t1 links may coexist within the s/uni-ima-84. additionally, for cell delineation only, atm over fractional t1/e1 is supported by allowing individual ds0 timeslots to be configured as active or inactive. ima is a protocol designed to combine the transport bandwidth of multiple links into a single logical link. the logical link is called a group. the s/uni-ima-84 can support up to 42 independent groups with each group capable of supporting 1 to 32 links. any link that is not participating in an ima group can utilize the cell
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 37 delineation features of the s/uni ima-84 for implementing either atm over e1 or atm over t1. in the transmit direction, the s/uni-ima-84 accepts cells from the any- phy/utopia interface. the s/uni-ima-84 performs the ima function which consists of taking a cell stream destined for a group and distributing the cells in a round-robin fashion to the links within a group, adding ima control protocol (icp) cells, filler cells, and stuff cells as needed. the icp cells convey state information to the far end and are used to format an ima frame. the ima frame is used as a mechanism to synchronize the links at the far end. cell rate decoupling is performed at the ima sub-layer via filler cells. filler cells are used instead of physical layer cells for cell rate decoupling, thus a continuous stream of cells is sent to the tc layer. the stuff cells are used to maintain synchronization between the links in a group by absorbing the rate differential when links are running on different clocks. the data from the ima sub-layer is passed on to the tc layer. in the tc layer, the hec is calculated and inserted into the cell headers and optional scrambling of the payload is performed. the cell stream is then mapped into the t1 or e1 payload with zeros inserted for the framing and overhead bits or bytes. the links are then transmitted via either the high density sbi interface or the clock and data interface. the s/uni-ima-84 acts as a clock slave ? i.e., the clock is provided from logic external to the s/uni-ima-84. an optional common-clock mode is provided to enable all links to run from the same clock. if using an unchannelized clock and data interface, the data is not mapped into the t1/e1 payload but is transmitted one bit for each provided clock pulse. on the receive side, the framed data is received from either the sbi or the clock/data interface, and the atm cell data is extracted from the t1, e1 or ds3 frame structure. if using an unchannelized clock and data interface, the data is received one bit for each provided clock pulse. the tc layer searches for cell delineation as per the procedures outlined in itu- t recommendation i.432.1. once cell delineation is obtained, the payload is optionally descrambled and the cells are passed to the ima sub-layer. the tc layer provides counts of errored headers as well as ocd and lcd error interrupts. the receive ima sublayer performs ima-frame delineation and stuff-cell removal. based upon the icp cell information, the s/uni-ima-84 determines the
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 38 differential delay between the links within a group and applies the link and group state machine logic to coordinate the activation and deactivation of groups and links with the far end. as cells are received, they are stored in an external fifo structure; this structure is based upon the ima frame boundaries and the ima frame sequence number. when links or groups are determined to be active by the link and group state machines, the data is played out to the any- phy/utopia interface at a constant rate to mimic the existence of a single higher bandwidth physical link. once a group of links is established, links can be added or deleted from the group. under software control, the s/uni-ima-84 will perform all necessary steps to add or delete links from previously established groups. in order to aid diagnostics, a line side loopback and a utopia side loopback are provided. also, an icp cell trace feature is provided. when the icp cell trace has been enabled for a group, the s/uni-ima-84 will place those icp cells where a scci field change is detected into a buffer that is accessible to the microprocessor.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 39 8 pin diagram the s/uni-ima-84 is packaged in a 416-pin pbga package that has a body size of 27mm by 27mm and a ball pitch of 1mm.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 40 figure 4 - s/uni-ima pinout (bottom view)
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 41 9 pin description 9.1 receive slave atm interface (any-phy mode) (28 signals) pin name type pin no. function rclk input w24 the receive clock (rclk) signal is used to transfer data blocks from the s/uni-ima-84 across the receive any-phy interface. the rpa, rsop, rsx, rdat[15:0], and rprty outputs are updated on the rising edge of rclk. the renb, radr[4:0], and rcsb inputs are sampled on the rising edge of rclk. the rclk input must cycle at a 52 mhz or lower instantaneous rate. rpa tristate output ab24 the receive packet available (rpa) is an active high signal that indicates whether at least one cell is queued for transfer. the s/uni-ima-84 device drives the rpa with the cell availability status two rclk cycles after radr[4:0] matches the s/uni ima?s device address. the rpa output is high-impedance at all other times. the rpa output is updated on the rising edge of rclk. renb input ab26 the receive enable bar (renb) is an active low signal used to initiate the transfer of cells from the s/uni-ima-84 to an atm layer component, such as a traffic management device. the renb input is sampled on the rising edge of rclk.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 42 pin name type pin no. function radr[4] radr[3] radr[2] radr[1] radr[0] input aa25 aa23 aa24 aa26 y25 the receive address (radr[4:0]) signals are used to address the s/uni-ima-84 device for the purposes of polling and selection for cell transfer. the radr[4:0] signals are valid only when the rcsb signal is sampled active in the following rclk cycle. the radr[4:0] input bus is sampled on the rising edge of rclk. rcsb input y24 the receive chip select (rcsb) is an active low signal that is used to select the s/uni-ima-84 receive interface. when the rcsb is sampled low, it indicates that the radr[4:0] sampled at the previous clock is a valid address. if the rcsb is sampled high, the device is not selected and the radr[4:0] sampled on the previous cycle is not a valid address and is ignored. when sufficient address space is provided by radr[4:0] for all devices on the bus, this signal may be tied low. the rcsb input is sampled on the rising edge of rclk. rsop tristate output w25 the receive start of packet (rsop) is an active high signal that marks the start of the cell on the rdat[15:0] bus. when rsop is active, the first word of the cell is present on the rdat[15:0] bus. the rsop output is updated on the rising edge of rclk. rsx tristate output w23 the receive start of transfer (rsx) signal is an active high signal that marks the first cycle of a data block transfer on the rdat[15:0] bus. when the rsx signal is active, the coinciding data on the rdat[15:0] bus represents the in-band phy address. the rsx output is updated on the rising edge of rclk.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 43 pin name type pin no. function rdat[15] rdat[14] rdat[13] rdat[12] rdat[11] rdat[10] rdat[9] rdat[8] rdat[7] rdat[6] rdat[5] rdat[4] rdat[3] rdat[2] rdat[1] rdat[0] tristate output w26 v25 v26 u25 v24 u26 u23 t25 u24 t26 r25 r26 t24 p25 r23 p26 the receive cell data (rdat[15:0]) signals carry the atm cell words that have been read from the s/uni-ima-84 internal cell buffers. when this interface is operating in 8-bit mode, the data is carried on rdat[7:0]. the rdat[15:0] output bus is updated on the rising edge of rclk. rprty tristate output n25 the receive parity (rprty) signal provides the parity (programmable for odd or even parity) of the rdat[15:0] bus. when the interface is operating in 8-bit mode, the parity is calculated over rdat[7:0] the rprty output is updated on the rising edge of rclk.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 44 9.2 receive slave atm interface (utopia l2 mode) (26 signals) pin name type pin no. function rclk input w24 the receive clock (rclk) signal is used to transfer data blocks from the s/uni-ima-84 across the receive utopia l2 interface. the rca, rsoc, rdat[15:0], and rprty outputs are updated on the rising edge of rclk. the renb and radr[4:0] inputs are sampled on the rising edge of rclk. the rclk input must cycle at a 52 mhz or lower instantaneous rate. rca tristate output ab24 the receive cell available (rca) is an active high signal that, when polled using the radr[4:0] signals, indicates if at least one cell is queued for transfer on the selected logical channel fifo . the s/uni-ima-84 device drives rca with the cell availability status for the polled port one rclk cycle after a valid radr[4:0] address is sampled. the rca output is high-impedance at all other times. the rca output is updated on the rising edge of rclk. renb input ab26 the receive enable bar (renb) is an active low signal used to initiate the transfer of cells from the s/uni-ima-84 to an atm-layer component, such as a traffic management device. the renb input is sampled on the rising edge of rclk. radr[4] radr[3] radr[2] radr[1] radr[0] input aa25 aa23 aa24 aa26 y25 the receive address (radr[4:0]) signals are used to address the s/uni-ima-84 device for the purposes of polling and selecting for cell transfer. the radr[4:0] input bus is sampled on the rising edge of rclk.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 45 pin name type pin no. function rsoc tristate output w25 the receive start of cell (rsoc) is an active high signal that marks the first word of the cell on the rdat[15:0] bus. the rsoc output is updated on the rising edge of rclk. rdat[15] rdat[14] rdat[13] rdat[12] rdat[11] rdat[10] rdat[9] rdat[8] rdat[7] rdat[6] rdat[5] rdat[4] rdat[3] rdat[2] rdat[1] rdat[0] tristate output w26 v25 v26 u25 v24 u26 u23 t25 u24 t26 r25 r26 t24 p25 r23 p26 the receive cell data (rdat[15:0]) signals carry the atm cell words that have been read from the s/uni-ima-84 internal cell buffers. when this interface is operating in 8-bit mode, the data is carried on rdat[7:0]. the rdat[15:0] output bus is updated on the rising edge of rclk. rprty tristate output n25 the receive parity (rprty) signal provides the parity (programmable for odd or even parity) of the rdat[15:0] bus. when the interface is operating in 8-bit mode, the parity is calculated over rdat[7:0] the rprty output is updated on the rising edge of rclk.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 46 9.3 transmit slave interface (any-phy mode) (34 signals) pin name type pin no. function tclk input f25 the transmit clock (tclk) signal is used to transfer cells across the any-phy interface to the internal downstream cell buffers. the tpa output is updated on the rising edge of tclk. the tenb. tsx, tsop, tdat[15:0], tprty, tadr[10:0], and tcsb inputs are sampled on the rising edge of tclk. the tclk input must cycle at a 52 mhz or lower instantaneous rate. tpa tristate output n26 the transmit packet available (tpa) is an active high signal that indicates the availability of space in the selected logical channel fifo when polled using the tadr[10:0] signals. the s/uni-ima-84 device drives tpa with the cell availability status of the polled port two tclk cycles after tadr[10:0] matches the s/uni ima?s device address. the tpa output is high-impedance at all other times. the tpa output is updated on the rising edge of tclk. tenb input p24 the transmit enable bar (tenb) is an active low signal that is used to indicate cell transfers to the internal cell buffers. the tenb input is sampled on the rising edge of tclk.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 47 pin name type pin no. function tadr[10] tadr[9] tadr[8] tadr[7] tadr[6] tadr[5] tadr[4] tadr[3] tadr[2] tadr[1] tadr[0] input m25 n24 m26 l25 m24 l26 m23 k25 l24 k26 k23 the transmit address (tadr[10:0]) signals are used to address logical channels for the purpose of polling and device selection. the tadr[10:0] signals are valid only when the tcsb signal is sampled active in the following tclk cycle. the tadr[10:0] input bus is sampled on the rising edge of tclk. tcsb input j25 the transmit chip select (tcsb) is an active low signal that is used to select the s/uni-ima-84 transmit interface. when the tcsb is sampled low, it indicates that the tadr[10:0] sampled at the previous clock is a valid address. if the tcsb is sampled high, the device is not selected and the tadr[10:0] sampled on the previous cycle is not a valid address and is ignored. when sufficient address space is provided by tadr[10:0] for all devices on the bus, this signal may be tied low. the tcsb is asserted low one cycle after a valid address is present on the tadr[10:0] signals. the tcsb input is sampled on the rising edge of tclk. tsop input k24 the transmit start of packet (tsop) is an active high signal that marks the start of the cell on the tdat[15:0] bus. when tsop is active, the first word of the cell is present on the tdat[15:0] bus. the tsop output is sampled on the rising edge of tclk.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 48 pin name type pin no. function tsx input j26 the transmit start of transfer (tsx) signal is an active high signal that marks the first cycle of a data- block transfer on the tdat[15:0] bus. when the tsx signal is active, the coinciding data on the tdat[15:0] bus represents the in-band phy address. the tsx output is sampled on the rising edge of rclk. tdat[15] tdat[14] tdat[13] tdat[12] tdat[11] tdat[10] tdat[9] tdat[8] tdat[7] tdat[6] tdat[5] tdat[4] tdat[3] tdat[2] tdat[1] tdat[0] input h25 h26 j24 g25 h23 g26 h24 f23 f26 g24 e25 e26 f24 d25 e23 d26 the transmit cell data (tdat[15:0]) signals carry the atm cell octets that are transferred to the internal cell buffer. when this interface is operating in 8-bit mode, only tdat[7:0] is used. the tdat[15:0] input bus is sampled on the rising edge of tclk. tprty input e24 the transmit parity (tprty) signal provides the parity (programmable for odd or even parity) of the tdat[15:0] bus. the tprty signal is considered valid only when valid data and inband address are transferring as indicated by the tenb signal asserted low. when this interface is operating in 8- bit mode, this signal provides the parity of tdat[7:0]. a parity error is indicated by a status bit and a maskable interrupt. the tprty input signal is sampled on the rising edge of tclk.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 49 9.4 transmit slave interface (utopia l2 mode) (26 signals) pin name type pin no. function tclk input f25 the transmit clock (tclk) signal is used to transfer cells across the any-phy interface to the internal downstream cell buffers. the tca output is updated on the rising edge of tclk. the tenb, tsoc, tdat[15:0], tprty, tadr[4:0] inputs are sampled on the rising edge of tclk. the tclk input must cycle at a 52 mhz or lower instantaneous rate. tca tristate output n26 the transmit cell available (tca) is an active high signal that indicates the availability of space in the selected logical channel fifo when polled using the tadr[4:0] signals. the s/uni-ima-84 drives tca with the cell space availability status for the polled port on tclk cycles after a valid tadr[4:0} address is sampled. the tca output is high-impedance when not polled. the tca output is updated on the rising edge of tclk. tenb input p24 the transmit enable bar (tenb) is an active low signal that is used to indicate cell transfers to the internal cell buffers. the tenb input is sampled on the rising edge of tclk. tadr[4] tadr[3] tadr[2] tadr[1] tadr[0] input m23 k25 l24 k26 k23 the transmit address (tadr[4:0]) signals are used to address logical channels for the purposes of polling and device selection. the tadr[4:0] input bus is sampled on the rising edge of tclk.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 50 pin name type pin no. function tsoc input k24 the transmit start of cell (tsoc) is an active high signal that marks the first word of the cell on the tdat[15:0] bus. the tsoc input is sampled on the rising edge of tclk. tdat[15] tdat[14] tdat[13] tdat[12] tdat[11] tdat[10] tdat[9] tdat[8] tdat[7] tdat[6] tdat[5] tdat[4] tdat[3] tdat[2] tdat[1] tdat[0] input h25 h26 j24 g25 h23 g26 h24 f23 f26 g24 e25 e26 f24 d25 e23 d26 the transmit cell data (tdat[15:0]) signals carry the atm cell octets that are transferred to the internal cell buffer. the tdat[15:0] signals are considered valid only when the tenb signal is asserted low. when this interface is operating in 8- bit mode, only tdat[7:0] is used. the tdat[15:0] input bus is sampled on the rising edge of tclk. tprty input e24 the transmit parity (tprty) signal provides the parity (programmable for odd or even parity) of the tdat[15:0] bus. the tprty signal is considered valid only when valid data is transferring as indicated by the tenb signal asserted low. when this interface is operating in 8-bit mode, this signal provides the parity of tdat[7:0]. a parity error is indicated by a status bit and a maskable interrupt. the tprty input signal is sampled on the rising edge of tclk.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 51 9.5 microprocessor interface (31 signals) pin name type pin no. function d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] i/o b19 d19 a19 c19 b18 a18 b17 c18 a17 d17 b16 a16 b15 a15 c16 b14 the micro data (d[15:0]) signals provide a data bus to allow the s/uni-ima-84 device to interface to an external microprocessor. both read and write transactions are supported. the microprocessor interface is used to configure and monitor the s/uni- ima-84 device. a[10] a[9] a[8] a[7] a[6] a[5] a[4] a[3] a[2] a[1] input d15 a14 c15 b13 a13 c14 b12 c13 a12 b11 the micro address (a[10:1]) signals provide an address bus to allow the s/uni-ima-84 device to interface to an external microprocessor. the a[10:1] indicate a word address. the s/uni- ima-84 microprocessor interface is not byte addressable. the a[10:1] input signals are sampled while the ale is asserted high. ale input c12 the address latch enable (ale) is an active high signal that latches the a[10:1] signals during the address phase of a bus transaction. when ale is set high, the address latches are transparent. when ale is set low, the address latches hold the address provided on a[10:1]. the ale input has an internal pull-up resistor.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 52 pin name type pin no. function wrb input a11 the write strobe bar (wrb) is an active low signal that qualifies write accesses to the s/uni-ima-84 device. when the csb is set low, the d[15:0] bus contents are clocked into the addressed register on the rising edge of wrb. rdb input d12 the read strobe bar (rdb) is an active low signal that qualifies read accesses to the s/uni-ima-84 device. when the csb is set low, the s/uni-ima-84 device drives the d[15:0] bus with the contents of the addressed register on the falling edge of rdb. csb input b10 the chip select bar (csb) is an active low signal that qualifies read/write accesses to the s/uni-ima- 84 device. the csb signal must be set low during read and write accesses. when the csb is set high, the microprocessor-interface signals are ignored by the s/uni-ima-84 device. if the csb is not required (register accesses are controlled only by wrb and rdb), then it should be connected to an inverted version of the rstb signal. intb open- drain output c11 the interrupt bar (intb) is an active low signal indicating that an enabled bit in the master interrupt register was set. when intb is set low, the interrupt is active and enabled. when intb is tristate, there is no interrupt pending or it is disabled. intb is an open drain output and should be pulled high externally with a fast resistor. maximum output current (imax) = tbd ma
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 53 9.6 sdram i/f (35 signals) pin name type pin no. function cbcsb output ad9 the cell buffer sdram chip select bar (cbcsb) is an active low signal used to control the sdram. cbcsb, cbrasb, cbcasb, and cbweb define the command being sent to the sdram. the cbcsb output is updated on the rising edge of sysclk. cbrasb output af10 the cell buffer sdram row address strobe bar (cbrasb) is an active low signal used to control the sdram. cbcsb, cbrasb, cbcasb, and cbweb define the command being sent to the sdram. the cbrasb output is updated on the rising edge of sysclk. cbcasb output ac10 the cell buffer sdram column address strobe bar (cbcasb) is an active low signal used to control the sdram. cbcsb, cbrasb, cbcasb, and cbweb define the command being sent to the sdram. the cbcasb output is updated on the rising edge of sysclk. cbweb output ae11 the cell buffer sdram write enable bar (cbweb) is an active low signal used to control the sdram. cbcsb, cbrasb, cbcasb, and cbweb define the command being sent to the sdram. the cbweb output is updated on the rising edge of sysclk.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 54 pin name type pin no. function cba[11] cba[10] cba[9] cba[8] cba[7] cba[6] cba[5] cba[4] cba[3] cba[2] cba[1] cba[0] output ad10 af11 ae12 af12 ad11 ae13 ac12 af13 ad12 ae14 ad13 ae15 the cell buffer sdram address (cba[11:0]) signals identify the row address (cba[11:0]) and column address (cba[7:0]) for the locations accessed. the cba[11:0] output is updated on the rising edge of sysclk. cbbs[1] cbbs[0] output ad14 af15 the cell buffer sdram bank select (cbbs[1:0]) signals determine which bank of a dual/quad bank cell buffer sdram chip is active. cbbs is generated along with the row address when cbrasb is asserted low. the cbbs[1:0] outputs are updated on the rising edge of sysclk. cbdqm output ae16 the cell buffer sdram input/output data mask (cbdqm) signal is held high until the sdram initialization is complete and then set low for normal operation. the cbdqm output is updated on the rising edge of sysclk.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 55 pin name type pin no. function cbdq[15] cbdq[14] cbdq[13] cbdq[12] cbdq[11] cbdq[10] cbdq[9] cbdq[8] cbdq[7] cbdq[6] cbdq[5] cbdq[4] cbdq[3] cbdq[2] cbdq[1] cbdq[0] i/o ad15 af16 ac15 ae17 ad16 af17 ac17 ae18 ad17 af18 af19 ad18 ae20 ac19 af20 ad19 the cell buffer sdram data (cbdq[15:0]) signals interface directly with the cell buffer sdram data ports. the cbdq[15:0] bi-directional signals are sampled and updated/tristated on the rising edge of sysclk.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 56 9.7 clk/data (129 signals) pin name type pin no. function tsclk[31] tsclk[30] tsclk[29] tsclk[28] tsclk[27] tsclk[26] tsclk[25] tsclk[24] tsclk[23] tsclk[22] tsclk[21] tsclk[20] tsclk[19] tsclk[18] tsclk[17] tsclk[16] tsclk[15] tsclk[14] tsclk[13] tsclk[12] tsclk[11] tsclk[10] tsclk[9] tsclk[8] tsclk[7] tsclk[6] tsclk[5] tsclk[4] tsclk[3] tsclk[2] tsclk[1] tsclk[0] input a23 b22 d22 c22 a21 b20 a20 c20 b9 c10 a9 b8 c9 b7 d8 a7 c8 b6 d6 a6 b3 c4 a3 a2 e3 f2 f4 f3 f1 g2 g1 g3 the transmit serial clock (tsclk[31:0]) signals contain the transmit clocks for the 32 independently timed links. the tsdata[31:0] signals are updated on the falling edge of the corresponding tsclk[31:0] clock. for channelized t1 or e1 links, tsclk[n] must be gapped during the framing bit (for t1 interfaces) or during time-slot 0 (for e1 interfaces) of the tsdata[n] stream. the s/uni- ima-84 uses the gapping information to determine the time-slot alignment in the transmit stream. for unchannelized links, tsclk[n] must be externally gapped during the bits or time-slots that are not part of the transmission format payload (i.e., not part of the atm cell). the tsclk[31:0] input signal is nominally a 50% duty cycle clock of 1.544 mhz for t1 links and 2.048 mhz for e1 links. the tsclk[31:0] may operate at higher rates in the unchannelized mode. at higher rates, the amount of lines available is limited. see 12.3.2.2 for more details.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 57 pin name type pin no. function tsdata[31] tsdata[30] tsdata[29] tsdata[28] tsdata[27] tsdata[26] tsdata[25] tsdata[24] tsdata[23] tsdata[22] tsdata[21] tsdata[20] tsdata[19] tsdata[18] tsdata[17] tsdata[16] tsdata[15] tsdata[14] tsdata[13] tsdata[12] tsdata[11] tsdata[10] tsdata[9] tsdata[8] tsdata[7] tsdata[6] tsdata[5] tsdata[4] tsdata[3] tsdata[2] tsdata[1] tsdata[0] output c25 d24 c26 b26 a22 b21 d21 c21 c7 b5 a5c6 b4 d5 a4 c5 d3 d1 e2 e4 b1 c2 c1 d2 h4 h1 h3 j2 j1 k2 j3 k1 the transmit serial data (tsdata[31:0]) signals contain the transmit data for the 32 independently timed links. for channelized links, tsdata[n] contains the 24 (t1) or 31 (e1) time- slots that comprise the channelized link. tsclk[n] must be gapped during the t1 framing bit position or the e1 frame alignment signal (time-slot 0). the s/uni-ima-84 uses the location of the gap to determine the channel alignment on tsdata[n]. for unchannelized links, tsdata[n] contains the atm cell data. for certain transmission formats, tsdata[n] may contain place holder bits or time- slots. tsclk[n] must be externally gapped during the place holder positions in the tsdata[n] stream. the tsdata[31:0] output signals are updated on the falling edge of the corresponding tsclk[31:0] clock
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 58 pin name type pin no. function rsclk[31] rsclk[30] rsclk[29] rsclk[28] rsclk[27] rsclk[26] rsclk[25] rsclk[24] rsclk[23] rsclk[22] rsclk[21] rsclk[20] rsclk[19] rsclk[18] rsclk[17] rsclk[16] rsclk[15] rsclk[14] rsclk[13] rsclk[12] rsclk[11] rsclk[10] rsclk[9] rsclk[8] rsclk[7] rsclk[6] rsclk[5] rsclk[4] rsclk[3] rsclk[2] rsclk[1] rsclk[0] input ac25 ad26 ad25 ae26 ac22 af23 ae23 ad21 ac21 ae21 ad8 af8 ad6 ac6 ad1 ac3 ae7 af6 ad5 ac5 ad4 ae4 ad2 ab3 ab1 ab2 y3 aa1 y2 v3 w1 w2 the receive serial clock (rsclk[31:0]) signals contain the recovered line clock for the 32 independently timed links. the rsdata[31:0] signals are sampled on the rising edge of the corresponding rsclk[31:0] clock. for channelized t1 or e1 links, rsclk[n] must be gapped during the framing bit (for t1 interfaces) or during time-slot 0 (for e1 interfaces) of the rsdata[n] stream. the s/uni- ima-84 uses the gapping information to determine the time-slot alignment in the receive stream. rsclk[31:0] is nominally a 50% duty cycle clock of 1.544 mhz for t1 links and 2.048 mhz for e1 links. for unchannelized links, rsclk[n] must be externally gapped during the bits or time-slots that are not part of the transmission format payload (i.e., not part of the atm cell). the rsclk[31:0] input signal is nominally a 50% duty cycle clock of 1.544 mhz for t1 links and 2.048 mhz for e1 links. the rsclk[31:0] may operate at higher rates in the unchannelized mode. at higher rates, the amount of lines available is limited see 12.3.2.2 for more details.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 59 pin name type pin no. function rsdata[31] rsdata[30] rsdata[29] rsdata[28] rsdata[27] rsdata[26] rsdata[25] rsdata[24] rsdata[23] rsdata[22] rsdata[21] rsdata[20] rsdata[19] rsdata[18] rsdata[17] rsdata[16] rsdata[15] rsdata[14] rsdata[13] rsdata[12] rsdata[11] rsdata[10] rsdata[9] rsdata[8] rsdata[7] rsdata[6] rsdata[5] rsdata[4] rsdata[3] rsdata[2] rsdata[1] rsdata[0] input ab23 ab25 ac26 ac24 af25 af24 ad23 ae24 ad20 af21 af9 ae9 ad7 af7 af3 ae3 ac8 ae8 ae6 af5 ae5 af4 af2 ae1 ac1 ab4 ac2 aa3 aa4 aa2 y1 w4 the receive serial data (rsdata[31:0]) signals contain the recovered line data for the 32 independently timed links. for channelized links, rsdata[n] contains the 24 (t1) or 31 (e1) time-slots that comprise the channelized link. rsclk[n] must be gapped during the t1 framing bit position or the e1 frame alignment signal (time-slot 0). the s/uni-ima-84 uses the location of the gap to determine the channel alignment on rsdata[n]. for unchannelized links, rsdata[n] contains the atm cell data. for certain transmission formats, rsdata[n] may contain place-holder bits or time- slots. rsclk[n] must be externally gapped during the place-holder positions in the rsdata[n] stream. the rsdata[31:0] input signals are sampled on the rising edge of the corresponding rsclk[31:0] clock.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 60 pin name type pin no. function ctsclk input h2 the common transmit serial clock (ctsclk) signal is a common transmit line clock that can optionally be used by all 32 serial links instead of each link?s transmit serial line clock (tsclk[n]). ground if not used. the ctsclk input signal is nominally a 50% duty cycle clock of 1.544 mhz for t1 links and 2.048 mhz for e1 links. 9.8 sbi interface signals (27) pin name type pin no. function dc1fp input p3 the active high drop bus c1 frame pulse (c1fp) signal is externally generated to indicate the first c1 octet of each four-frame sbi multiframe on the drop bus. this frame pulse is a single refclk cycle long and is sampled on the rising edge of refclk. this signal should be pulsed once every fourth c1 octet to produce a 2 khz multiframe signal. the frame pulse does not need to be repeated every fourth sbi frame. the s/uni-ima-84 will synchronize to this signal and flywheel in its absence. ddata[7] ddata[6] ddata[5] ddata[4] ddata[3] ddata[2] ddata[1] ddata[0] input r4 u2 t3 u1 u4 v2 u3 v1 the drop bus data (ddata[7:0]) signals are a time division multiplexed bus which transports tributaries by assigning them to fixed octets within the sbi bus structure. multiple phy devices can drive this bus at uniquely assigned tributary columns within the sbi bus structure. the ddata[7:0] input signals are sampled on the rising edge of refclk.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 61 pin name type pin no. function ddp input r1 the drop bus data parity (ddp) signal carries the even or odd parity for the drop bus signals. the parity calculation encompasses ddata[7:0], dpl, and dv5 signals. the selection of even or odd parity is made via the sbi_par_ctl bit of sbi extract control register. multiple phy-devices can drive this signal at uniquely assigned tributary columns within the sbi bus structure. this parity signal is intended to detect multiple sources in the column assignment. the ddp input signal is sampled on the rising edge of refclk. dpl input t2 the active high drop bus payload (dpl) is an active high signal that indicates valid data within the sbi bus structure. this signal is asserted during all octets making up a tributary. this signal goes high during the v3 octet within a tributary to accommodate negative timing adjustments between the tributary rate and the fixed sbi bus structure. this signal goes low during the octet after the v3 octet within a tributary to accommodate positive timing adjustments between the tributary rate and the fixed sbi bus structure. multiple phy-devices can drive this signal at uniquely assigned tributary columns within the sbi bus structure. the dpl input signal is sampled on the rising edge of refclk.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 62 pin name type pin no. function dv5 input t1 the active high drop bus payload indicator (dv5) is an active high signal that locates the position of the floating payloads for each tributary within the sbi bus structure. timing differences between the port timing and the sbi bus timing are indicated by adjustments of this payload pointer relative to the fixed sbi bus structure. multiple phy-devices can drive this signal at uniquely assigned tributary columns within the sbi bus structure. all movements indicated by this signal must be accompanied by appropriate adjustments in the dpl signal. the dv5 input signal is sampled on the rising edge of refclk. ac1fp input r2 the active high add bus c1 frame pulse (c1fp) signal is externally generated to indicate the first c1 octet of each four-frame sbi multiframe on the add bus. this frame pulse is a single refclk cycle long and is sampled on the rising edge of refclk. this signal should be pulsed once every fourth c1 octet to produce a 2 khz multiframe signal. the frame pulse does not need to be repeated every fourth sbi frame. the s/uni-ima-84 will synchronize to this signal and flywheel in its absence. adata[7] adata[6] adata[5] adata[4] adata[3] adata[2] adata[1] adata[0] tristate output m2 m1 l3 n2 m4 n1 m3 p2 the add data (adata[7:0]) signals are a time division multiplexed bus which transports tributaries by assigning them to fixed octets within the sbi bus structure. the s/uni-ima-84 drives adata[7:0] only at uniquely assigned tributary columns within the sbi bus structure. the adata[7:0] output signals are updated on the rising edge of refclk.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 63 pin name type pin no. function adp tristate output l1 the add bus data parity (adp) signal carries the even or odd parity for the add bus signals. the parity calculation encompasses adata[7:0], apl and av5 signals. the selection of even or odd parity is made via sbi_par_ctl bit of sbi insert control register. the s/uni-ima-84 drives adp only at uniquely assigned tributary columns within the sbi bus structure. the adp output signal is updated on the rising edge of refclk. apl tristate output k3 the active high add bus payload (apl) is an active high signal that indicates valid data within the sbi bus structure. this active high signal is asserted during all octets making up a tributary. this signal goes high during the v3 or h3 octet within a tributary to accommodate negative timing adjustments between the tributary rate and the fixed sbi bus structure. this signal goes low during the octet after the v3 or h3 octet within a tributary to accommodate positive timing adjustments between the tributary rate and the fixed sbi bus structure. the s/uni-ima-84 drives the apl only at uniquely assigned tributary columns within the sbi bus structure. the apl output signal is updated on the rising edge of refclk.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 64 pin name type pin no. function av5 tristate output l2 the active high add bus payload indicator (av5) is an active high signal that locates the position of the floating payload for each tributary within the add bus structure. the s/uni-ima-84 drives av5 only at uniquely assigned tributary columns within the sbi bus structure. all movements indicated by this signal are accompanied by appropriate adjustments in the apl signal. the av5 output signal is updated on the rising edge of refclk. ajust_re q input p1 the active high add bus justification request (ajust_req) signal is used to speed up or slow down the s/uni-ima-84 which is sending data to the phy (e.g., temux). this active high signal indicates negative timing adjustments when asserted high during the v3 or h3 octet, depending on the tributary type. in response to this, the s/uni-ima-84 will send an extra byte in the v3 or h3 octet of the next frame. this signal indicates positive timing adjustments when asserted high during the octet following the v3 or h3 octet, depending on the tributary type. the s/uni-ima-84 will respond to this by not sending an octet during the v3 or h3 octet of the next frame. all timing adjustments from the s/uni-ima-84 in response to the justification request will still set the payload and payload indicators appropriately for timing adjustments. the ajust_req input signal is sampled on the rising edge of refclk.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 65 pin name type pin no. function aactive output k4 the add bus active indicator (aactive) is an active high signal that is asserted during all octets when driving data and control signals - adata[7:0], adp, apl and av5 ? onto the add bus. all other sbi link layer devices (e.g., other s/uni- ima-84s on the sbi bus) driving the add bus listen to this signal to detect multiple sources driving the add bus, which can occur due to configuration problems the aactive output is asserted on the rising edge of refclk. adetect input n3 the add bus active detector (adetect) signal indicates when another device is driving the add bus. other link layer device aactive outputs can be externally or?ed together and connected to adetect. when the s/uni-ima-84 is driving aactive high and simultaneously detects adetect is high, it tristates its add bus outputs to minimize or eliminate contention. adetect is an asynchronous signal which is used to disable the tristate drivers on the add bus. the and of aactive and adetect is used. to indicate that a collision has occurred. this input must be tied low when not used. 9.9 general (5 signals) pin name type pin no. function rstb input ae22 the reset bar (rstb) is an active low signal that provides an asynchronous s/uni-ima-84 reset. rstb is a schmitt-triggered input with an internal pull-up resistor.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 66 pin name type pin no. function oe input af22 the output enable (oe) is an active high signal that allows all of the outputs of the device to operate in their functional state. when this signal is low, all outputs of the s/uni-ima-84 go to the high impedance state, with the exception of tdo . sysclk input ae10 the system clock (sysclk) signal is the master clock for the s/uni-ima-84 device. the core s/uni- ima-84 logic (including the sdram interface) is timed to this signal. external sdram devices share this clock and must have clocks aligned within 0.2ns skew of the clock seen by the s/uni-ima-84 device. this clock must be stable prior to deasserting rstb 0->1. sysclk must cycle at a 50-55 mhz instantaneous rate to support the maximum number of links (84 t1, 63 e1 or 3 ds3). refclk input r3 sbi_mode:the reference clock (refclk) signal is an externally generated 19.44mhz +/-50ppm clock with a nominal 50% duty cycle. refclk is common to both the add and drop sides of the sbi bus. in clk/data mode, refclk is required and may be operated at frequencies up to 52 mhz. in general, for t1 and e1 links, 33 mhz is sufficient. see 12.3.2.3 for details on selecting the proper frequency. nc ad22 no connect. this signal ball is not connected to the die.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 67 9.10 jtag & scan interface (7 signals) pin name type pin no. function tck input a25 the test clock (tck) signal provides timing for test operations that are carried out using the ieee p1149.1 test access port. tms input b24 the test mode select (tms) is an active high signal that controls the test operations carried out using the ieee p1149.1 test access port. the tms signal has an integral pull-up resistor. the tms input is sampled on the rising edge of tck. tdi input a24 the test data input (tdi) signal carries test data into the s/uni-ima-84 via the ieee p1149.1 test access port. the tdi signal has an integral pull-up resistor. the tdi input is sampled on the rising edge of tck. tdo tristate b23 the test data output (tdo) signal carries test data out of the s/uni-ima-84 via the ieee p1149.1 test access port. tdo is a tristate output that is inactive except when the scanning of data is in progress. the tdo output is updated/tristated on the falling edge of tck. trstb input c23 the active low test reset (trstb) is an active low signal that provides an asynchronous s/uni-ima-84 test access port reset via the ieee p1149.1 test access port. trstb is a schmitt-triggered input with an integral pull-up resistor. note that when not being used, trstb must be connected to the rstb input. scan_mode b input a10 the active low scan mode (scan_modeb) is an active low signal that places the s/uni-ima-84 into a manufacturing test mode. must be tied high to disable the scan logic.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 68 pin name type pin no. function scanenb input d10 the active low scan enable ( scanenb) is an active low signal that enables the internal scan logic for production testing. must be tied high to disable the scan logic. 9.11 power (120 signals) pin name type pin no. function vddi (1.8 v) power e1 w3 af14 ae19 y26 r24 c17 a8 the core power pins (vddi[7:0]) should be connected to a well-decoupled +1.8 v dc supply.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 69 vss (vssi, vsso, vssq) ground a1,a26 b2,b25 c3,c24 d4,d9 d13,d14 d18,d23 j4,j23 n4,n23 p4,p23 v4,v23 ac4,ac9 ac13 ac14 ac18 ac23 ad3,ad24 ae2,ae25 af1,af26 k10,k11 k12,k13 k14,k15 k16,k17 l10,l11 l12,l13 l14,l15 l16,l17 m10,m11 m12,m13 m14,m15 m16,m17 n10,n11 n12,n13 n14,n15 n16,n17 p10,p11 p12,p13 p14,p15 p16,p17 r10,r11 r12,r13 r14,r15 r16,r17 t10,t11 t12,t13 t14,t15 t16,t17 u10,u11 vss the vss pins should be connected to gnd. vsso pins are ground pins for ports. vssq pins are ?quiet? ground pins for ports. vssi pins are core ground pins. all grounds should be connected together.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 70 vdd (3.3v) power d7 d11 d16 d20 g4 g23 l4 l23 t4 t23 y4 y23 ac7 ac11 ac16 ac20 vdd (3.3v) the i/o power pins (vdd) should be connected to a well-decoupled +3.3 v dc supply. these pins include the vddo pins for the switching, as well as the vddq for the quiet power pins. notes on pin description: ? all s/uni-ima-84 i/o present minimum capacitive loading and operate at ttl logic levels and can tolerate 5.0v levels. ? inputs rstb, ale, tck, tms, tdi and trstb, tsclk, ctsclk, rsclk, rsdata, an oe have internal pull-up resistors. ? power to the vdd (3.3v) pins should be applied before power to the vddi (1.8v) pins is applied. similarly, power to the vddi (1.8v) pins should be removed before power to the vdd (3.3v) pins is removed.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 71 10 functional description this section describes the function of each entity in the s/uni-ima-84 block diagram. throughout this document the use of the term ?transmit? implies data read in from the cell interface and sent out the lineside interface. conversely, ?receive? is used to describe the data path from the lineside interface to the cell interface. the term ?virtual phy? refers to a single flow on the any-phy/utopia bus. each ima group or a single tc connection is mapped to a virtual phy. for simplicity, both an ima group and a tc connection will be referenced as a group. each ima group can map data to/from multiple links. each tc group is mapped to a single link. the term ?link? refers to either: (1) a t1, e1, or ds3 link that is multiplexed onto the sbi bus or (2) a single t1/e1 link or unchannelized link on the clock/data interface. when supporting fractional t1/e1 via the clock/data interface, the timeslots that are chosen to be part of the fractional connection are also referred to as a link. within the clock/data interface, the external links are mapped to a contiguous space identified as virtual links. to support multiple fractional tc flows on a single external signal, a mapping is used to split a single channelized external signal into multiple virtual links. at the per-link fifos, the clock/data virtual link naming convention is used synonymously with the physical link naming convention. 10.1 any-phy/utopia interfaces the atm cell interfaces are any-phy compliant 8/16 bit slave interfaces which are compatible with the following options: ? any-phy slave ? utopia level 2, 31-port slave (multi-phy-mode) ? utopia level 2, single port slave (single address mode) for receive side only.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 72 10.1.1 transmit any-phy/utopia slave (txaps) in the transmit direction, each s/uni-ima-84 receives cells on the any- phy/utopia l2 compatible interface operating at clock rates up to 52 mhz and supporting 16-bit and 8-bit wide cells. the s/uni-ima-84 operates as a bus slave only. cell transfers are cell-based, that is, an entire cell is transferred from one phy device before another is selected. polling occurs concurrently with cell transfers to ensure maximum throughput. data pausing is not supported in any-phy mode. if the tenb is deasserted prior to a complete cell being transferred, the cell transfer error interrupt will be triggered. 10.1.1.1 utopia level 2 multi-address slave mode in the utopia level 2 multi-address slave mode, the transmit interface of the s/uni-ima-84 appears as a 31 port multi-phy. an 11-bit configuration register tcaen (only 4 bits are used in ul2 mode) controls the response to polling the individual channels within this group of 31 ports. setting high on tcaen[0] enables addresses 0 through 7, and tcaen[3] enables addresses 24 through 30. this is typically used to allow more than one slave device to share the transmit any-phy/utopia master bus. for utopia l2 mode, only 31 ports are available, using 31 independent fifos. utopia l2 mode limits the s/uni-ima-84 to 31 ima groups or tc links. only tadr[4:0] are used for polling and selection. each fifo will only assert tca when polled if it is not in the process of transferring a cell and if there is room in the fifo for a complete cell. unlike any-phy, in utopia mode the virtual phy port must first be selected prior to the start of the data transfer. this selection is done using the same address lines that are used for polling in combination with the tenb pin. 10.1.1.2 any-phy slave mode in the any-phy slave mode, the transmit interface of the s/uni-ima-84 appears as a multi-phy device with 84 ports used for the data path where all ports are identified in the in-band address. the configuration register tcaen controls the response to polling the individual channels within this group of 84 ports. setting high on tcaen[0] enables addresses 0 through 7, and tcaen[3] enables addresses 24 through 31. this is typically used to allow more than one slave device to share the transmit any-phy/utopia master bus.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 73 conceptually, the any-phy protocol can be divided into two processes: polling and cell transfer. polling in the transmit direction is used by the bus master ? typically a traffic buffering and management device ? to determine when a buffered data cell can be safely sent to a phy. the s/uni-ima-84 provides an independent 3-deep cell buffer fifo for each virtual phy. in total, there are 84 fifos. this arrangement ensures that there is no head-of-line blocking, while providing latitude to the master for servicing high data rate ports as well as low data rate ports. the traffic manager need only poll those virtual phys for which it has cells queued. a cell transfer can be initiated after a polled virtual phy asserts the tpa output. each virtual phy?s cell buffer availability status (i.e., the status that will be driven onto the tpa output when the virtual phy is polled) is deasserted when the first byte of the last cell is written into the buffer. it is re-asserted only when the fifo can accept another complete cell. in any-phy mode, polling is performed using the tadr[10:0] bus in conjunction with the tcsb. each s/uni-ima-84 uses the tadr[6:0] bits to indicate the 84 logical virtual phys. the upper bits from the tadr bus, tadr[10:7], are compared to the configured address to select the device. the remaining address bits from the traffic manager are decoded externally and are used to drive the tcsb. the address prepend field in the cell transfer contains the entire 16-bit address. in 8-bit mode, the prepend address is reduced to 8-bits. in any-phy mode, the cell transfer is initiated after a successful poll. the virtual phy address is prepended to the cell, thus performing an inband selection. the s/uni-ima-84 monitors the address prepend on the cell transfer to detect its cells. 10.1.1.3 transmit cell transfer format the transmit cell transfer format is shown in figure 5 and figure 6. word/byte 0 is required for cell transfers to an any-phy slave. the address prepend is the s/uni-ima-84 virtual phy id. the virtual phy id can be mapped to a tc link or to an ima group. optional prepends are supported, but are ignored by the s/uni- ima-84. inclusion of optional words is statically configurable for the interface. the optional words are always ignored.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 74 figure 5 - 16-bit transmit cell transfer format bits 15-8 bits 7-0 word 0 (any-phy only) address prepend word 1 (optional) optional prepend word 2 h1 h2 word 3 h3 h4 word 4 hec/udf word 5 payload1 payload2 word 6 payload3 payload4 ?? ? ? ? ?? ? ? ? ? ? ? ?? ? ? ? word 28 payload47 payload48 figure 6 - 8-bit transmit cell transfer format bits 7-0 byte 0 (any-phy only) address prepend byte 1 (optional) optional prepend[15:8] byte 2 (optional) optional prepend[7:0] byte 3 h1 byte 4 h2 byte 5 h3
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 75 byte 6 h4 byte 7* hec byte 8 payload1 ? ? ? ? ? ? ? ? ? byte 55 payload48 10.1.2 receive any-phy/utopia slave (rxaps) in the receive direction, each s/uni-ima-84 transmits cells on an any- phy/utopia l2 compatible interface operating at clock rates up to 52 mhz and supporting 16-bit and 8-bit wide cells. the s/uni-ima-84 operates as a bus slave. in all modes, an optional prepend is allowed on the bus. this prepend will always be set to zero and has no significance to the s/uni ima-84 but is provided for interoperability. 10.1.2.1 utopia level 2 multi-address slave mode in utopia level 2 multi-address slave mode, the s/uni-ima-84 operates as a 31 port multi-phy with each virtual phy stored in its own fifo. utopia l2 mode limits the s/uni-ima-84 to 31 ima groups or tc links. a 4-bit configuration register, rcaen, controls the response to polling the individual channels within this group of 31 ports. setting rcaen[0] enables addresses 0 through 7, and rcaen[3] enables addresses 24 through 30. this is typically used to allow more than one slave device to share the receive utopia master bus. when polled, the receive packet available (rpa) output indicates whether there is at least one cell available for transfer from the polled link. upon selection, the interface handles data pausing anywhere in the middle of a cell transfer.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 76 10.1.2.2 utopia level 2 single-address slave mode in utopia level 2 single address slave mode, the s/uni-ima-84 operates as a single device with a single large 124 cell fifo, with all cells being identified by their virtual phy id (vphy id) in an address prepend. each ima or tc connection is limited to a maximum of 16 cells in the fifo. the address prepend may be optionally mapped to the hec/udf field in order to maintain the standard cell length. when the address presented on the any-phy/utopia interface radr pins matches a programmable 5-bit configuration register (devid), the rxaps will respond to polls. in all other cases, the output signals are tristated which allows other slave devices to respond. when polled, the rpa output indicates whether there is at least one cell available for transfer from any link. 10.1.2.3 any-phy slave mode in any-phy slave mode, the s/uni-ima-84 operates as a single device with a single large 124 cell fifo, with all cells being identified by their virtual phy id (vphy id) in a address prepend. each ima or tc connection is limited to a maximum of 16 cells in the fifo. when the address presented on the any- phy/utopia interface radr pins matches a programmable 5-bit configuration register (devid), the rxaps will respond to polls. in all other cases, the output signals are tristated which allows other slave devices to respond. when polled, the rpa output indicates whether there is at least one cell available for transfer from any link. in any-phy mode, data pausing is not supported. to support current and future atm layer devices, the cell interface is configurable as either an any-phy or utopia l2 interface. table 2 summarizes the distinctions between the two protocols. table 2 utopia l2 and any-phy comparison attribute utopia l2 any-phy latency rdat[15:0], rprty, and rsop are driven or become high impedance immediately upon sampling renb low or high, respectively. the rpa is driven with the cell availability status one clk cycle after the radr[4:0] rdat[15:0], rprty, rsop and rsx are driven or become high impedance on the rclk rising edge following the one that samples renb low or high, respectively. the rpa is driven with the cell
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 77 pins match the s/uni-ima- 84?s address. a match is defined as either matching the programmed value in single phy mode or being within the correct range for multi-phy mode. availability status two clk cycles after radr[4:0] pins match the s/uni-ima-84?s address. rsx undefined. it is low when not high impedance. high coincident with the first word of the cell data structure. rsop high coincident with the first word of the cell data structure. high coincident with the first byte of the cell header. paused transfers permitted by deasserting renb high, but the s/uni- ima?s address must be presented on radr[4:0] the last cycle renb is high to reselect the same phy. not permitted. autonomous deselection not supported. a subsequent cell is output (provided one is available) if renb is held low beyond the end of a cell. the outputs become high impedance after the last word of a cell is transferred and until the s/uni-ima-84 is reselected. 10.1.2.4 receive cell transfer format the cell format for the receive direction is the same as the transmit interface; see figure 7 and figure 8 for the formats.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 78 figure 7 - 16-bit receive cell transfer format bits 15-8 bits 7-0 word 0 (any-phy and single channel ul2 only*) address prepend word 1 (optional) optional prepend word 2 h1 h2 word 3 h3 h4 word 4* hec/udf word 5 payload1 payload2 word 6 payload3 payload4 ?? ? ? ? ?? ? ? ? ? ? ? ?? ? ? ? word 28 payload47 payload48 note: address prepend for single channel ul2 may be inserted in hec/udf field instead of prior to the cell. figure 8 - 8-bit receive cell transfer format bits 7-0 byte 0 (any-phy and single channel ul2 only*) address prepend byte 1 (optional) optional prepend[15:8]
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 79 byte 2 (optional) optional prepend[7:0] byte 3 h1 byte 4 h2 byte 5 h3 byte 6 h4 byte 7* hec byte 8 payload1 ? ? ? ? ? ? ? ? ? byte 55 payload48 note: address prepend for single channel ul2 may be inserted in hec/udf field instead of prior to the cell for any-phy mode or single-phy mode, the address prepend field encoding indicates the virtual phy id. the virtual phy id contains 2 sections, the lower 7 bits indicates the virtual phy id with valid values for 0 to 83, while the upper bits are user programmable and not used by the device but may be required in a user?s system for unique device identification when multiple devices exist on a bus. for utopia multi-phy mode, the address prepend is not used. 10.1.3 summary of any-phy/utopia modes the following table summarizes the available modes of the any-phy/utopia interfaces mode dir & protocol ul2 single phy ul2 multi-phy any-phy tx poll not supported phy channels: 31 phy channels: 84 channel enable register: channel enable register:
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 80 tcaen(3:0) tcaen(10:0) channel address pins: tadr(4:0) device id register: cfg_addr(10:7) status pin: tca channel address pins: tadr(6:0) device address pins: tadr(10:7) address qualifier pin: tcsb status pin: tca tx select not supported phy channels: 31 phy channels: 84 channel enable register: tcaen(3:0) channel enable register: tcaen(10:0) channel address pins: tadr(4:0) device id register: cfg_addr(15:7) or (7) select pin: tenb channel address: prepend bits (6:0) device address: prepend bits (bit 15:7, for 16 bit mode) or (bit 7 for 8-bit mode) select pin: tenb tx transfer not supported cell size: 8 bit x 53 or 55 bytes cell size: 8 bit x 54 or 56 bytes cell size: 16 bit x 27 or 28 words cell size: 16 bit x 28 or 29 words enable pin: tenb enable pin: tenb, tsx to indicate first byte of transfer. pause in cell: w/ tenb rx poll phy channels: 1 phy channels: 31 phy channels: 1 (in-band addressing is used to identify virtual phys) device id register: devid(4:0) channel enable register: rcaen(3:0) device id register: devid(4:0) device address pins: radr(4:0) channel address pins: radr(4:0) device address pins: radr(4:0) status pin: rca status pin: rca status pin: rca rx select phy channels: 1 phy channels: 31 phy channels: 1 device id register: devid(4:0) channel enable register: rcaen(3:0) device id register: devid(4:0) device address pins: radr(4:0) channel address pins: radr(4:0) device address pins: radr(4:0) select pin: renb select pin: renb select pin: renb rx transfer cell size: 8 bit x 53, 54, 55 or 56 bytes cell size: 8 bit x 53 or 55 bytes cell size: 8 bit x 54 or 56 bytes cell size: 16 bit x 27, 28 or 29 words cell size: 16 bit x 27 or 28 words cell size: 16 bit x 28 or 29 words enable pin: renb enable pin: renb enable pin: renb channel address: prepend or udf pause in cell: w/ renb channel address: prepend
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 81 10.1.4 any-phy/utopia loopback for diagnostic purposes, the capability to loopback all any-phy/utopia traffic back to the any-phy/utopia bus is provided. cells are taken from the transmit group fifos and placed into the respective receive group fifos, or to a single fifo on a space available basis. if the receive interface is in any-phy or single address utopia l2 mode, all tx ports are looped back to the respective rx port. if the receive interface is in multiple port utopia l2 mode and the transmit any- phy is configured in 84-port any-phy mode, the 84 transmit ports will be aliased onto the 31 receive ports. transmit port numbers 31 and 63 will be blocked and are not functional for loopback operations. 10.2 ima sub-layer 10.2.1 overview the ima protocol provides inverse multiplexing of a single atm stream over multiple physical links and reassembles the original cell stream at the far-end. the inverse multiplexing is performed on a cell basis; hence, the ima protocol is described as a cell-based protocol. see figure 9 below. the protocol is based upon the concept of an ima frame. an ima frame is programmable in size and is delineated by an ima control protocol (icp) cell. it is recommended that the icp cells of each link in the ima group be offset from each other to reduce the notification time of link/group status changes. the transmitter is responsible for aligning the ima frames on all links within a group, and for ensuring that cells are transmitted continuously by adding filler cells as necessary. to maintain frame alignment in the presence of independently timed line clocks, a cell based stuffing algorithm is utilized. since the ima frames are aligned on transmission, this allows the receive end to recover the ima frames and align them to remove any differential delay between the physical links.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 82 figure 9 - inverse multiplexing physical link #1 physical link #0 ima group ima group ima virtual link phy phy phy original cell stream passed to atm layer phy phy physical link #2 single atm cell stream from atm layer phy tx direction cells distributed across links in round robin sequence rx direction cells recombined into single atm stream 10.2.2 idcc scheduler the ima data cell clock (idcc) scheduler calculates the ima data cell rate (idcr) for each group that is used by both the receive and the transmit ima processors. there is one scheduler for each direction (txidcc and rxidcc), and each scheduler can monitor the rate of up to 84 reference clocks; each scheduler can also generate up to 84 idcc clocks based upon idcr. for each group, the reference link can be selected to be one of the 84 monitored links. each of the monitored links can only be the reference link for one group. idcr is calculated using the following equation, with n on and m set independently for each idcr generator. n on is the number of active links, m is the size of the ima frame, and trl cell rate (trlcr) is the cell rate of the reference link. idcr = n on x trlcr x (m-1/m) x (2048/2049) trlcr is generated from the byte rate. the byte rate is obtained by monitoring the data transfers on the internal bus in the tc layer. for each idcr clock tick, a service request is generated and placed into a rate based fifo. since there may be many requests generated in a short amount of time and the rate at which each request is generated may be different, a method is required to arbitrate between the requests to prevent blocking of high rate requests by large numbers of low rate requests. to achieve this, each request is placed into a priority fifo. the priority of the request is based upon its rate.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 83 there are a total of 5 rate-based fifos. when a service request is accepted by the transmit ima processor (tima) or the receive ima data processor (rdat), the next request to be presented is taken from the highest priority fifo that has an entry. in this manner, the higher rate requests get higher priority than the lower rate requests. since the s/uni-ima-84 can always service all of the requests, this algorithm limits the cdv experienced by any service request to approximately one inter-arrival time of the service request for each group. rate changes are restricted to ima frame boundaries. an ima frame boundary occurs once every (m-1)*n service requests. when a request is received to change the rate(n on ), the request is saved until the next ima frame boundary, at which point it takes effect. by restricting rate changes to frame boundaries, the rate accuracy is preserved preventing fifo underflows/overflows. since rate changes are not instantaneous, a vector that represents the active link ids (lids) in the group is passed with the service request. in this manner, the entity receiving the service requests is informed of the change in rate and of which links should currently be in the round robin for servicing. all ima-based rate changes are internally managed by the s/uni-ima-84; no user interaction is necessary for correct scheduling. the idcc is also used for scheduling the tc data flow. in this case, the rate generated is simply the cell rate of the tc link and is not modified for ima icp cells or stuff cells according to the following equation: idcr = trlcr for all tc connections, the idcc must be configured in tc mode for the physical link. 10.2.3 transmit ima processor (tima) the tima is responsible for the transmit ima functions. this consists of distributing the cells arriving from the atm layer to links in a group and for inserting icp cells, filler cells, and stuff cells as required by the ima protocol. additionally, the tima can support cell transmission on connections using only the transmission convergence (tc) sublayer without the use of the ima protocol sublayer.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 84 10.2.3.1 ima frame the transmit ima processor creates the ima frame by inserting an icp cell after every (m-1) cells per link. values of m supported are 32, 64, 128, and 256. the icp cell is offset within the ima frame. this offset is programmable on a per-link basis, and the offsets should spread throughout the frame. to avoid interaction between groups, the offsets within a group may not be aligned at the same offset. if offsets are aligned at the same offset within a group, the cdv experienced by other groups will be increased. each frame is identified with an ima frame sequence number (ifsn); this number is the same for every link in the group that is within the same frame and increments with each frame. the tima is responsible for aligning the transmission of the ima frame on all links within a group. 10.2.3.2 stuffing procedure the tima can support both independent transmit clock (itc) and common transmit clock (ctc) modes. the difference between these modes is the stuffing protocol. the method of stuffing is set independently from the clocking mode present in the icp cell. in ctc mode, a stuff cell is added after 2048 cells on each link. the stuff cell is identical to the icp cell and is inserted immediately following the icp cell. the stuff cell events will occur on the same frame on all links; however, the programmed icp offsets determine at which cell in the frame the stuff event will occur. in itc mode, a stuff cell is added to the reference link after 2048 cells on the reference link. on all other links in the group, stuff cells are added as necessary to compensate for data rate differences between the link and the reference link of the group. the added stuff cells (or lack of stuff cells) keep the data rate between links equalized. the stuff cell is generated immediately after the icp cell and both the icp cell and the stuff cell are identified as stuff cells via the link stuff indication (lsi) field of the icp cell. in ctc mode, the stuff event is always advertised in the icp cell of the preceding frame. the stuff event may also be advertised in the 4 preceding frames. it is programmable per group whether the icp cell is advertised starting 1 frame or 4 frames prior to the occurrence of the stuff event.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 85 in itc mode, the stuff event may be advertised in the icp cell of the preceding frame or in the four preceding frames. if the stuff event needs to be advertised for four preceding frames, a ds1/e1 clock tolerance of +/- 50 ppm, or better, is required. if a frequency tolerance of +/- 50 ppm cannot be met among the independent transmit clocks, the tima can provide the single frame advertisement of stuff events. to determine when a stuff cell is needed on itc mode links (not the trl), a link stuff detection unit with rate counters is used to track the relative rate of data being read from the link fifos within a group to the rate of data being read from the trl fifo for the same group. when the relative rate counter indicates that the rate differences have accounted for a slip of a cell, a stuff cell is inserted. 10.2.3.3 data flow the tima can support up to 84 groups (ima group or tc link). each fifo on the atm-layer interface side represents either an ima group or a tc group. each group?s behavior is controlled by the internal memory tables and records. for ima groups, the following internal memory structures are used: 1) the transmit ima group configuration record for configuring group options and mapping to a port on the atm interface (vphy id) 2) transmit ima group context record contains statistics and the current icp cell image. 3) transmit lid to the physical link mapping table is used to map individual physical links into a group and assign the lids.. 4) tima physical link context record contains per-link statistics, and state information. for tc links, only one record is used, the transmit physical link record, to maintain statistics and to map the physical link to a port on the atm interface (vphy id). the tima performs cell transfers from the group fifos to the link fifos in response to service requests from the txidcc. the txidcc schedules both ima groups, as well as low and high rate (ds3) tc-only connections. groups are scheduled according to their rates. higher-rate groups are prioritized above the lower-rate groups. the tima operates at a rate sufficient to ensure the txidcc will not suffer request congestion provided the icp cells are spread throughout
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 86 the frame on ima groups. if there is no service request pending, the tima remains idle. if a group is unused, no cells will be pulled from the respective group fifo. therefore, when de-activating groups, atm cell flow to the s/uni- ima-84 should be terminated prior to de-activating the group in order to prevent stale data from being stored in the group fifo. 10.2.3.3.1 ima service for each ima group-service request, a cell is transferred from the group fifo to one of the link fifos. if no cell is available from the group fifo, an ima filler cell is generated and placed in the link fifo. the link fifos within a group are serviced in a round-robin fashion, with the round-robin order determined by the lid. if the next link in the round robin is due to receive an icp cell, the icp cell is generated using the link and group state information from the transmit ima group context record, and the lid and lsi from the link. if a stuff event is scheduled, the stuff icp cell is also inserted. whenever an icp cell is inserted, the ima group servicing proceeds to the next link in the round robin without waiting for another service request. the ima group service is complete when either: (1) a cell is transferred from the group fifo or (2) an atm filler cell is generated. when links are in the process of being added, but are not yet available for carrying data traffic, ima frames consisting of filler cells and icp cells are generated. such links are not scheduled by the txidcc scheduler, but will be processed with the currently active links. during group start-up, even with all of the transmit links in the unusable state, the txidcc scheduler is started and ima frames are generated. during group start-up (i.e. links are not yet in the active state), a group can be configured such that cells received via the utopia l2 / any-phy bus can be dropped to avoid the accumulation of stale data or to drop stale data in the group fifo left over from a previous use of the vphy id. . during link additions, ima frames are generated on new links when they are added to the group. 10.2.3.3.2 tc only service for tc-only mode groups, servicing is also initiated by group service requests from the txidcc. however, servicing a group fifo simply entails transferring a cell from the group fifo to the proper link fifo. if a cell is not present in the group fifo, no cells are transferred and the servicing of the request is complete. in tc mode, no other cells are inserted into the data stream by the ima sub-layer (physical layer idle cells are generated by the physical layer).
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 87 10.2.3.4 timing reference link maintenance it is possible to have the timing reference link for an ima group change from one link to another while the ima connection is in operation. if an ima group is operating in ctc mode, the reference link used for the scheduling is simply switched. the next stuff cell insertion still occurs 2049 cells after the previous stuff. if the ima group is operating in itc mode and the reference link is switched, the first stuff insertion on the new trl occurs at approximately the same frame a stuff would have been inserted had it not become the trl. at the time of the trl change, the existing accrued rate differential on the new trl is used to prorate the number of cells out of 2048 until the next trl stuff. although the first stuff will occur at approximately the proper number of cells to maintain the correct differential delay, the actual time of the stuff will be dependent on the new trl rate. similarly, the first stuff cell insertion on the previous trl occurs in approximately the same frame a stuff cell would have been inserted had it still been the trl although the actual frame for stuff insertion will also be dependent on the rate difference with the new trl. this minimizes any effects on the differential delay for the group as well as reducing any fifo level changes. all subsequent stuff cell insertions on the trl then happen after every 2048 cells and all subsequent stuff cell insertions on the former trl are dependent only on the link?s rate difference from the new trl. 10.2.4 receive ima data processor (rdat) the receive ima data processor (rdat) performs the ima data-flow functions in the receive direction including the ima frame synchronization mechanism (ifsm), storage of data for accommodating differential delay, defect detection, and playout of data in a round robin fashion. the number of links and the differential delay tolerance required determine the sdram size used for the delay compensation buffers (dcb). two configurations of sdram are supported: 16 mbit (1 mbit x 16) and 64 mbit (4 mbit x 16), both are available as single chip devices. differential-delay tolerance may be configured through registers on a per-group basis to any value up to the maximum listed in figure 10. buffering is allocated on a per link basis. each link is allocated the same number of cell buffers. either 256 or 1024 cell buffers may be allocated per link. see figure 10 for the required memory sizes.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 88 figure 10 - max differential delay tolerance vs. sdram size # of t1/e1 links cells of buffering delay (t1) in ms delay (e1) in ms sdram size 32 t1/ 32 e 1 1024 279 ms 226 ms 1mbit x16 84 t1/ 63 e 1 256 69 ms 56 ms 1mbit x16 84 t1 / 63 e 1024 279 ms 226 ms 4mbit x16 10.2.4.1 writing data to the delay compensation buffers (dcb) when there is a full cell of data in the rx link fifos, the link requests service. in order to support ds3 rates, the synchronous payload envelope (spe) concept is carried over from the sbi interface. the link fifos are divided into 3 groups where each group is given 1/3 of the bandwidth. the rdat arbitrates between links requiring service within each group. if a group does not use its priority bandwidth, it is made available to the next group. this arbitration also works with the clock/data interface since all links should be close in rate. when a link is chosen for service, if it is not an ima link, the cells are stored in external memory in a per link fifo. for ima links, the ifsm is performed to locate the ima frame. once the ima frame is located, the rdat calculates the location to store the cells. the cells are stored in a time-based fifo structure. the buffer address for a cell is created from the cell number in the ima frame concatenated with the lower x (depends upon m) bits of the ima frame sequence number. each link has its own reserved fifo. the cells are stored in this manner such that they are aligned in time in the external memory and the differential-delay removal is simplified. during periods in which the link is in a defect state, incoming cells will be replaced with filler cells prior to being written to the dcb. 10.2.4.2 ima frame synchronization mechanism (ifsm) for ima links, the rdat performs the ifsm. the ifsm is based upon the cell delineation mechanism in i.432. the details of the ifsm can be found in af-phy- 0086.001 ?inverse multiplexing for atm (ima) specification version 1.1?, march 1999. the state machine is shown in figure 11.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 89 figure 11 - ifsm state machine missin g icp cell = == = consecutive invalid icp cells = == = consecutive errored icp cells ima sync ( frame b y frame ) = == = consecutive valid icp cells one valid icp cells ima hunt ( cell b y cell ) one invalid or errored/missing icp cell ima presync ( frame b y frame ) starting state v alid icp at unex p ected p osition ( with cell b y cell huntin g) valid icp at unexpected position (with cell by cell hunting) during group start-up, the fields in the icp cells are validated by the rx ima protocol processor (ripp) block and the validated information is used to determine whether the icp cells are valid or not. validation by the ripp checks the group fields of the icp cell to ensure that they match the rest of the group and checks the lid to ensure that it is unique in the group. an icp cell is invalid if either the ima oam label, the lid, the ima_id, m, ifsn or the offset is not the same as the validated values. if the icp cell cannot be validated by the ripp (i.e. the ima_id is different from the rest of the group or the lid is a duplicate), the ifsm will remain in the starting state. once the icp cells are validated by the ripp, the ifsm will enter the ima hunt state. in this state, each cell will be examined to see if it is a valid icp cell. when a single valid icp cell has been received, the ifsm will enter the ima presync state. while in the presync state, at each expected icp location (determined by the icp offset and the ima frame length), the cell will be examined (frame by frame).
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 90 once gamma ( = ) = valid icp cells have been received, the ifsm will enter the ima sync state. if either: (1) an invalid (or errored) icp cell is received or (2) a valid icp cell is received in an unexpected location, the ifsm will re-enter the ima hunt state. while in the ima hunt state, the stuff indicators will be ignored. while in the ima sync state, icp cells are continually examined for each frame. if beta ( = ) = consecutive icp cells with hec, ocd, or crc-10 errors (errored icp cells) are received, then the ifsm will reenter the ima hunt state. also, if alpha ( = ) = consecutive invalid icp cells are received, the ifsm will reenter the ima hunt state. if a cell is received at the expected icp position without an hec error or ocd and without the ima oam cell header, or is a filler cell, it is considered a missing icp cell, and the ifsm will reenter the ima hunt state immediately. finally, if a valid icp cell is received at an unexpected position, the ifsm will re- enter the ima hunt state. alpha, beta, and gamma are globally programmable for the device. the rdat keeps working-counts for these parameters for each link. it should be noted that alpha (the count of consecutive invalid icp cells) will not be reset upon receipt of an errored cell; although beta (the count of consecutive errored icp cells) will be reset upon receipt of an invalid icp cell. 10.2.4.3 stuff events at this point, the rdat detects and removes the stuff cells. stuff cells are identified by the lsi field with the icp cells. stuff events consist of two back-to- back icp cells on the same link. one of the icp cells is considered a stuff cell. since stuff cells are inserted for the purpose of equalizing the data rate on links with independent clocks, stuff cells are removed. to improve robustness in the presence of errors, the transmitter is required to advertise that a stuff event is going to occur in the icp cell in the frame preceding the stuff event. the transmitter may also advertise the stuff event for the 4 frames preceding the stuff event. once a valid non-errored icp cell has been received with a lsi of 001, 010, 011, or 100, the rdat will maintain an internal stuff count in link-context memory. this count will be decremented every frame, until the stuff event occurs. the count will be decremented even if an incoming icp cell is errored or invalid (as shown in figure 12). an icp cell received with an invalid stuff sequence (i.e., lsi of 001, when a lsi of 010 was expected) will be declared invalid, and the internal stuff count will be decremented from the previous value (as shown in figure 13. the internal count is reset to the maximum when the stuff event occurs. a stuff
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 91 sequence of 111 followed by 000 is not considered an invalid stuff sequence (i.e., the rdat will always accept immediate notification of a stuff event, to support the case when the 001 stuff cell was errored). figure 12 - stuff event with errored icp (advanced indication) ifsn: ima frame sequence number lsi: link stuffing indication time m-1 filler or atm layer cells icp cell ifsn # i+4 lsi = 111 stuff event icp cell ifsn # i+3 lsi = 000 stuff_cnt =3 stuff_cnt =0 stuff_cnt =1 stuff_cnt =2 stuff_cnt =7 icp cell ifsn # i+3 lsi = 000 icp cell ifsn # i+2 lsi = 001 icp cell errored icp cell ifsn # i lsi = 011 figure 13 - invalid stuff sequence (advanced indication) ifsn: ima frame sequence number lsi: link stuffing indication time m-1 filler or atm layer cells icp cell ifsn # i+4 lsi = 111 stuff event icp cell ifsn # i+3 lsi = 000 stuff_cnt =3 stuff_cnt =0 stuff_cnt =1 stuff_cnt =2 stuff_cnt =7 icp cell ifsn # i+3 lsi = 000 icp cell ifsn # i+2 lsi = 001 icp cell ifsn #i+1 lsi=001 icp cell ifsn # i lsi = 011 10.2.4.4 ima frame synchronization with stuff events the rdat will maintain synchronization while receiving stuff events subjected to hec or crc errors, as shown in figure 14. when one of the icp cells comprising a stuff event is errored or invalid, the other will be used. if both are errored or invalid, then the internally maintained stuff count will be used to identify the stuff event (given that the advanced indicators were correct). all of the cases assume that the ifsm is in the ima sync state prior to the window shown, and that the current errored/invalid counts are zero. cases (1) through (6) require that alpha or beta be programmed to a value greater than one for synchronization to be maintained. case (7) requires that alpha or beta be
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 92 programmed to a value greater than two for synchronization to be maintained. case (7) also requires that advance link stuff indication be given prior to the window shown in order to detect the stuff event. figure 14 - errored/invalid icp cells in proximity to a stuff event stuf f e vent time icp n+1 icp icp ( 1 ) icp icp ( 2 ) icp icp ( 3 ) icp icp ( 4 ) icp icp ( 5 ) icp icp ( 6 ) icp icp ? ? ? ? ? ? ( 7 ) icp n icp icp icp icp icp icp icp m-1 filler or a tm la y er cells icp hec/crc errored or invalid icp cell
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 93 10.2.4.5 delay compensation buffers since ima must re-create the original cell stream in the proper order, delay compensation buffers (dcbs) are used to remove the differential delay between the links in a group. as cells arrive from each link, they are placed in that link?s dcb. links with the least transport delay will have the largest amount of data in the dcb, while links with the largest amount of transport delay will have the least amount of data in the dcb. at group start-up, all the links are compared to determine the link with the largest transport delay and the link with the least transport delay. the difference between these is the differential delay. data is queued for all links until the corresponding data arrives for the link with the largest transport delay. figure 15, shows a group with 3 links with a differential delay of 5 cells. link 0 has the shortest transport delay and link 2 has the longest transport delay. once the data has arrived for all of the links, it is played out to the atm layer at the idcc rate, thus keeping the depths of each dcb at a nominally constant level. (depths are instantaneously effected by the presence of stuff cells and icp cells, but these effects are transitory). figure 15 - snapshot of dcb buffers 1 7 10 13 16 19 4 dcb link 0 2 8 11 5 3 6 dcb link 1 dcb link 2 write pointer 0 write pointer 1 write pointer 2 group read pointer
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 94 when a group is already started, ima supports the addition of links to the group. as illustrated by figure 15, adding a link with a transport delay that is within the range of the existing links does not present any problems. the dcb for the new link must be aligned with the existing links and added to the round-robin for playout. adding a link with a smaller transport delay increases the differential delay of the group. this requires that the depth of the dcb buffer be larger than any of the existing links. as long as the differential delay is within acceptable bounds, the new link can be accepted. the dcb for the new link is aligned with the existing links and added to the round-robin for playout. figure 16 - snapshot of dcb buffers after addition of link with smaller transport delay 1 9 13 17 21 25 5 dcb link 0 2 10 14 6 3 7 dcb link 1 dcb link 2 write pointer 0 write pointer 1 write pointer 2 group read pointer 4 12 16 20 24 28 32 8 36 dcb link3 write pointer 3 adding a link with a larger transport delay requires the dcb buffer depth to be smaller than the dcb for the link with the largest delay. if the desired dcb depth for the new link is less than 0, this means that the data for the other links has been played out prior to the arrival of data for the new link. this is shown in figure 17. for the new link to be accepted, delay must be added to all other links in the group. when delay is added to the other links in the group, the playout of atm cells is halted until enough delay is built up. this causes cdv for the group.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 95 once the delay has been added, the dcb for the new link can be aligned with the existing links and added to the round-robin for playout. figure 18 shows the case after delay was added to the existing links within the group. the adding of delay to a group may be disabled. in this case, the new link would be rejected due to a lods defect meaning that the dcb could not be aligned with the group. figure 17 - snapshot of dcb buffers when trying to add link with larger transport delay 1 9 13 17 21 25 5 dcb link 0 2 10 14 6 3 7 dcb link 1 dcb link 2 write pointer 0 write pointer 1 write pointer 2 group read pointer dcb link3 write pointer 3 -5
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 96 figure 18 - snapshot of dcb buffers after delay adjustment 1 9 13 17 21 25 29 5 33 dcb link 0 2 10 14 18 22 6 3 11 15 7 dcb link 1 dcb link 2 write pointer 0 write pointer 1 write pointer 2 group read pointer 4 8 dcb link3 write pointer 3 when links are deleted from a group, the dcb buffer depths of the remaining links are not effected. as shown in figure 19, links 2 and 3 have been deleted from the group and the depth of the delay compensation buffers remain unchanged.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 97 figure 19 - snapshot of dcb buffers after deletion of links from group 1 5 7 9 11 13 14 3 15 dcb link 0 2 6 8 10 12 4 dcb link 1 dcb link 2 write pointer 0 write pointer 1 group read pointer dcb link3 removed from group removed from group 10.2.4.6 ima link error handling for ima operation, the rdat is responsible for detecting loss of ima frame defects (lif), idle cells on ima links, loss of cell delineation defects (lcd), and dcb overruns/underruns that contribute to loss of delay synchronization (lods). this information is forwarded to the ripp with the icp messages for processing and reporting. 10.2.4.6.1 ima error/maintenance state machine (iesm) a state machine is maintained for the lif defect detection. this state machine is called the ima error/maintenance state machine [iesm]. the state diagram for the iesm is shown in figure 20. the rdat maintains an iesm for each link. the lif defect state is the initial state for this process, thus all links will initially come up in the lif condition.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 98 figure 20 - ima error/maintenance state diagram ima working state out of ima frame (oif) anomaly state lif defect leaving ima sync state entering ima sync state persistence of non-ima sync ( +2) ima frames persistence of ima sync for at least 2 ima frames the ima working state enables the rdat to write user cells to the dcb. if the ifsm leaves the ima sync state, the iesm state machine will transition to the oif anomaly state, and the oif anomaly counter will be incremented. in the oif anomaly state, incoming user cells are written as filler cells to the dcb, and write pointers are incremented. if the ifsm does not return to the ima sync state within gamma + 2 frames, the iesm state will transition to the lif defect state. (gamma is programmable, and is the same gamma used in the ifsm). if the ima sync state is entered prior to gamma + 2 frames, the iesm state will transition back to the ima working state. this is considered a ?fast recovery? from the oif anomaly. in the lif defect state, incoming user cells are written as filler cells to the dcb, and write pointers are incremented. the lif-latched status bit will be set in the link-context memory. the iesm state machine will transition to the ima working state when ima sync has been detected for two consecutive ima frames. if the ima sync state is entered and then exited during lif, then the oif anomaly counter will be incremented. when the iesm enters the working state, user cells may be forwarded once again if an overrun (with respect to the configured depth for the link) is not detected. the overrun detection provides the necessary differential-delay checking required after a defect. 10.2.4.6.2 loss of cell delineation status (lcd) lcd is detected by the tc layer and the information is passed to the rdat. when a link is in lcd, a lcd-latched status bit is set in link context memory,
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 99 which is cleared by the icp cell processing procedure. cells received while the lcd latched status bit is set will be written to the dcb as filler cells, and the write pointers will be incremented. after an lcd condition is exited, the delay synchronization of the link must be rechecked and resynchronized. an lcd defect will cause the ifsm state machine to go into the hunt state to ensure the delay synchronization is rechecked. the transition of the ifsm into the hunt state will also cause an oif anomaly. 10.2.4.6.3 dcb overrun status when cells are written into the dcb, overruns will be checked by comparing the group read pointer against the link write pointer. if the difference between the pointers exceeds the maximum allowed dcb depth, then an overrun has been detected. for ima, this will cause the overrun latched status-in-link context to be set. an overrun condition will not cause the ifsm to exit the sync state. all user cells will be dropped while the overrun condition persists. the overrun condition is reset at the reception of an icp cell with an acceptable delay as long as the link is clear of lif or oif. for tc, an interrupt to the processor will be generated and normal operation will resume once the overrun condition has ended. 10.2.4.6.4 dcb underrun status when cells are read from the dcb, underruns will be checked by comparing the group read pointer against the link write pointer. when an underrun is detected, all user cells will be dropped until the underrun condition is cleared. the underrun condition will only be cleared at the reception of an icp cell, such that the differential delay may be re-checked. an underrun condition will not cause the ifsm to exit the sync state. 10.2.4.6.5 idle cells on ima links when idle cells are detected on an ima link, they will be reported. idle cells on ima links may be present for two reasons. they may have been inserted at the atm layer of the transmitter as a rudimentary method for traffic management; in which case the ima layer should treat them as user cells. otherwise, they may have been inserted at the tc layer to assist with rate matching; this is illegal for
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 100 ima links. idle cells will be treated as user cells by the rdat for ima processing and will not be dropped at the ima sub-layer. 10.2.4.7 dcb playout the idcc scheduler provides the rate for data to be played out to the atm layer for an ima group. for each cell to be played out, the idcc generates a service request. upon the idcc service request, the rdat plays out data from the fifos in a round-robin fashion. for each service request, the rdat runs the round robin servicing until it processes either a filler cell or user cell. if icp cells are encountered, the icp cell is dropped and the servicing continues until a user or filler cell is found. if a user cell is found, it is transferred from the external memory to the appropriate group fifo. if a filler cell is found, it is dropped. the rdat is not sensitive to the alignment of icp cells within a group. there is no performance degradation even if all of the icp cells in a group have the same offset. if the device is in any-phy mode or utopia l2 single port mode, there is only a single fifo shared among all of the groups. the rdat ensures that no more than 16 cells are stored in the shared fifo for a single group. if the s/uni-ima- 84 is in utopia l2 multi-port mode, each group has its own fifo. if the group fifo is not emptied in a timely fashion, data is dropped; this is similar to the procedure used by any other phy level device. the idcc service request fifo will always be serviced regardless of the state of the group fifo. for multi-port mode, if the respective group fifo is full, the cell will be dropped. in any-phy mode and utopia l2 single port mode, if either the shared fifo is full or there are already 16 cells for the current group in the fifo, the cell will be dropped. 10.2.5 receive ima protocol processor (ripp) the receive ima protocol processor (ripp) block is responsible for maintaining and controlling the link and group state machines. the ripp can accept commands from the management plane to initiate group and link state machine actions. the ripp then controls the contents of icp cells generated for the transmit data path, as well as analyzes the link and group states received within the icp cells. the receive link and group states are utilized to maintain and update the link and group states. the ripp coordinates group wide state transactions and performs the group wide procedures such as the synchronized link activation during group start-up procedure and the link addition and slow
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 101 recovery (lasr) procedure. when the links change state, the ripp also coordinates the rate change between the round-robin procedures located in the receive and transmit data paths and their respective rate schedulers. since failures are based upon the persistence of defects, the defects are detected and passed as interrupts/status to the management plane. pm is responsible for the integration of defects into failure conditions and to set the failure conditions in the s/uni-ima-84. table 3 pm command description command description add_group starts up a group state machine and the link state machines for the links configured in the group. group and links need to be configured prior to issuing this command. as a result of this command, the transmitter will start to send out ima frames on the links specified as part of the group, and the receiver will start to look for and analyze icp cells received on the links within the group. if a sufficient number of links are detected to be active, the group will transition to the operational state and start to transmit and receive atm traffic. delete_group remove an existing group and all its links immediately. this command will take the group state machine to the ?not configured? state and all of the links in the group to the ?not in group? state. the transmit links will cease to transmit ima frames and will commence to transmit physical-layer idle cells until the links are reused. for group deletion without any loss of data, the links may be deleted or inhibited to stop traffic on the group or the group may be inhibited prior to deleting the group.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 102 restart_group restart the specified group. when executed, the gsm goes back to ?start-up? state and all tx links return to the ?unusable? state and the rx links return to the ?unusable? state but report ?not in group? since the lid is not yet validated. this command is intended to enable the change of parameters during the group start-up phase and to provide a local group reset for other conditions. inhibit_group set the internal group inhibiting status flag. once a group is considered inhibited, it will go to blocked state instead of the operational state when sufficient links exist in the group. if the group is already in operational state when the command is issued, the gsm will go to blocked state, and thus block the tx data path. however, the rx data path remains on. not_inhibit_group clear the internal group inhibiting status. if the group is currently in blocked state, the gsm will go to operational state. start_lasr start lasr procedure on one or more links. the links involved may either be new links or existing links with a failure/fault/inhibiting condition. if the group configuration is symmetric, links should be added in both the tx and rx direction.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 103 delete_link remove one or more links from the group. if the group configuration is symmetric, links should be deleted in both the tx and rx directions. when a tx link is deleted, user traffic is no longer sent on the link and it?s state is reported as ?not in group?, but ima frames are still generated. when either a timeout expires or the fe rx is detected to be no longer active, the deleted links stop generating ima frames and start generating idle cells until the link is reused. when an rx link is deleted, it?s state is reported as ?not in group?, but traffic is still received and passed to the atm layer, until the either a timeout expires or fe tx state is detected to be no longer active. data received after this point will no longer be forwarded to the atm layer. the rx link is available for reuse after all the data accumulated in the dcb has been forwarded to the atm layer. no data will be lost in the link deletion procedure unless the timeout occurs prior to the fe state change detection. set_rx_phy_defect indicate to s/uni ima-84 that the given link(s) have/have not physical defects (such as los/lof/oof/ais) which are not detectable internally. this causes the s/uni-ima-84 to start reporting physical layer defects in the rx defect indication field in the icp field for the affected links.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 104 unusable_link force links to an unusable state and provide the cause. for rx links, if the cause is inhibited, the links are taken through the blocking state to preserve data sent prior the link being inhibited. if the cause is a fault or a failure condition, the link is taken directly to the unusable state. at this point, data would have already begun to be discarded due to the defects detected on the link. for tx links, data will stop being accepted on the unusable links and ima frames will be generated consisting of filler cells. update_test_ptn update the tx test pattern info to be sent in the outgoing icp cells. this command is used to activate, deactivate, or change the test pattern that is being sent out on the group. update_tx_trl update the transmit trl. when a trl is changed, three steps are performed: (1) the trl sent in the icp cell is changed;(2) the trl used for calculating the idcc is changed, and (3) the trl used in the stuffing algorithm is changed. read_event read and clear the latched event status, and read the link/group status of the specified group and all its links. the result read from the internal context memory is stored in cmd_data00 through cmd_data1f. refer to ripp command data registers for further details.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 105 read_delay reads a snapshot of the link-defect status and link-delay information for all of the links within the group. the delay information can be used to determine differential delay, the link with the most delay, and any other delay characteristics of the group. the delay information is provided in units of cells. adjust_delay adjusts the delay of a group by removing the amount of specified delay. while the delay is being adjusted, links cannot be added or recovered for the group. in addition to performing commands from pm, the ripp processes the icp cells forwarded by the rdat. when icp cells arrive from a group, they may be out of order in time due to differential delay between links. the ripp must examine the icp cell and determine if it has any new information that needs processing. this can be determined via the ima frame number and the ssci field. when processing the icp cells and the link states, attention must be taken not to violate the group wide procedures. when link or group states are changed, updated icp cells are sent to the tima for transmission. any state changes are also communicated to the appropriate schedulers and round-robin processors. 10.2.5.1 group start-up and differential delay on group start-up, when at least p rx links obtain ima frame synchronization, the links will be evaluated. as each link is evaluated, the differential delay of the accepted links is tracked. if a link cannot be accepted because the acceptance of the link would violate the programmed maximum dcb threshold (fastest link minus current data read pointer), the link will remain in the unusable state and begin to report a lods defect. accepted links will begin to report a usable state. at this point, as additional links acquire frame sync, they are evaluated and either are accepted or begin to report an lods defect. when all links have acquired frame sync or the timer has expired, the accepted receive links are reported as active. if at least p rx links have been accepted, the group state machine transitions to operational.. if sufficient links are not accepted, the group will not become operational. note that within any collection of links that are targeted to form an ima group the group may not become operational even though there are combinations of p rx links that meet the programmed maximum dcb threshold. this would occur in situations
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 106 where the internal algorithm used to determine link order may not select the combination or ?tightest? grouping of links that would otherwise meet the programmed maximum dcb threshold. in this case, the relative delays of the links are available to pm using the read_delay command. the microprocessor can then analyze this information, remove the offending link or links and restart the group. 10.2.5.2 link addition and differential delay once a group is started, the delay profile for the group is determined. in order to add links, the delay on the new links must be compatible with the existing links in the group and be able to be synchronized with the existing links within the dcb constraints. there are two mechanisms regarding delay that can be used. the first method uses the guardband capability. at group start-up, a guardband is added to the link with the longest transport delay. this guardband results in additional delay to be queued in the dcbs for each link in the group. the guardband allows for links with a longer transport delay to be added in the future without introducing any additional cdv. the second method allows the delay accumulated per link to be increased dynamically. this method will introduce additional delay to all of the links within the group when a link with a larger transport delay is added to the group. the process of adding additional delay to the links within a group will cause additional cdv to be introduced when the playout of data is stopped while the delay is accumulated. the ripp determines the delay of the links that are being added and performs the appropriate action to either include the link in the group or to reject the link if the link cannot be synchronized within the dcb constraints if a link is rejected due to delay, a lods defect will be reported on the link. when links are deleted from the group, the delay of the remaining links is not adjusted. see 10.2.4.5 for more details on the management of the dcb buffers.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 107 10.2.5.3 removing accumulated delay in some situations, removal of accumulated delay may be desired. this usually occurs after a group has been operational for a period of time and the link characteristics in terms of transport delay have changed. the adjust_delay command is provided to remove delay from the group. the execution of this command will effect the cdv of the group while the delay is reduced. any delay adjustment to the group will also effect the cdv of a connection carried on that group. this is additive, if 20 ms of delay is removed from the group, a particular connection within the group will experience an additional 20 ms of cdv. this will generally only be a concern to cbr or vbr-rt traffic flows. this increase in cdv may cause traffic to be policed out or real time applications to experience slips. to minimize the effect on the group traffic rate, while the delay is being reduced, the atm cells from the group will be transferred to the atm layer at a rate of (1+1/16)*idcr versus idcr. in other words, the group will playout data 6.25% faster to the atm layer during the process of delay reduction. the amount of time the delay removal takes depends upon the amount of delay to be removed. for example, a group where 200 ms of delay is to be removed takes approximately 3 seconds for the process to complete. while delay adjustments are being made to a group, new links can not be added and links can not be recovered from an error state. the s/uni-ima-84 will reject any requests to start a lasr procedure. however, while delay adjustments are in progress, links can be deleted or made unusable. 10.2.5.4 group start-up procedure when the add_group command is issued, the group state machine will enter the start-up state and start to send ima frames on the configured tx links. 10.2.5.4.1 start-up state while in the start-up state, the configured tx link state machines will be reporting the unusable state and the rx-link state machines will be reporting not_in_group. at this point, the s/uni-ima-84 will start to monitor the incoming icp cells. when icp cells are received with the fe indicating that the group is in start-up, the s/uni-ima-84 will transition to the start-up-ack state if the m value, the group symmetry, the oam label and ima_id (optional) values are acceptable. otherwise, the s/uni-ima-84 will transition into the config-aborted state.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 108 10.2.5.4.2 config-aborted state when entering the config-aborted state, a timer is started and an interrupt is generated. the s/uni-ima-84 will stay in the config aborted state until either: 1) the management plane restarts the group using the restart_group command. the restart can be done with either the same parameters or with different parameters. 2) the config-abort timeout expires. 10.2.5.4.3 start-up-ack state when entering the start-up-ack state, a timer is started. in the start-up-ack state, the s/uni-ima-84 waits for the fe to report the start_up_ack state. if the timer expires prior to the fe-reporting start_up_ack (or insufficient links, blocked, or operational states), the s/uni-ima-84 transitions back into the start_up state. otherwise, when the fe reports start-up-ack, the s/uni-ima-84 transitions to the insufficient links state. 10.2.5.4.4 insufficient links when in the insufficient links state, the start_lasr command should be executed to start the lasr procedure to bring up additional links the lasr procedure starts two timers; one for the tx links and one for the rx links. when the lasr procedure is complete (all links become active or timeout), if sufficient links are active, the group state machine transitions into the operational state unless the group is blocked. if sufficient links are not active after the lasr procedure completes, an interrupt is generated. since links will only transition into the active state via a lasr procedure, pm can activate a new lasr procedure with the same set of links and/or with additional links to bring up the group. 10.2.5.4.5 blocked and operational states while in the blocked and operational states, the link state machines are monitored to ensure that sufficient links stay active. if insufficient links are
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 109 detected active, the group state machine will transition into the insufficient links state and will stop accepting data from the atm layer for transmission. 10.2.5.5 lasr procedure links will only become active as part of the lasr procedure. the add_group command will automatically spawn a lasr procedure. to add links or recover links after group start-up, the start_lasr command should be used. if an lasr procedure is in progress, additional start_lasr commands will be rejected. 10.2.5.5.1 tx links when the lasr procedure starts, all tx links (participating in the lasr) in the unusable state or not_in_group state will immediately transition into the usable state if they are not faulted or inhibited. (note that the fe rx links may be reporting ?not in group? at this point since their lids have not been validated). links in other states will remain in the same state. if test patterns are to be transmitted on the links to test them prior to putting them in service, the tx links should be configured to be brought up with the inhibited state set. this keeps the tx links in the unusable state until they are released by a new lasr command (the pm_unusable status can only be cleared by a lasr). once the tx links start to report the usable state, a programmable timer is started. when either the timer expires or all of the fe rx links report the active state, the acceptable tx links will transition to the active state. this completes the lasr for the tx links. 10.2.5.5.2 rx links during the lasr procedure, the lids for the receive links are validated. until the lids are validated, the rx links report the ?not in group? state. as the lids are validated, the rx links start to report the unusable state. this transition is not synchronized with other links in the group. after all the receive links have their differential delay checked and have no defects (obtained ima frame sync) or a programmable timeout occurs, all of the accepted links will transition to the usable state. after the rx links are reported usable, another programmable timeout is started. once all of the links are reported tx_usable by the fe or the timeout expires,
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 110 the accepted links will start to report rx_active. if operating in symmetrical mode, the te tx links must be in the usable/active state in order for the accepted links to transition into rx_active. if some additional links have become usable since the last timeout, they will skip directly from the unusable to the active state. this completes the lasr for the rx links. when the lasr for both the rx and tx links is complete, the lasr procedure is complete. if the lasr completes due to a timeout and not all of the links are in the active state, an interrupt will be generated (if enabled) to inform pm that the links were not brought to the active state. 10.2.5.6 deactivating links links may be brought down by either pm or by the far end. pm may declare a fault on a link, inhibit a link, or delete the link. the far-end state changes may also cause the link to go down. this is the method of coordinating link deactivation between the ne and fe. 10.2.5.6.1 far end link deactivation if the fe tx states transition into an unusable state, the ne rx states go to the usable state and all data received prior to this point will be played out. if the fe rx states transition into a not active state, the ne tx link will transition into the usable state and stop transmitting data on that link. 10.2.5.6.2 near end (management) link deactivation if the ne rx link is removed from the group, the s/uni-ima-84 will transition to the deleted state until all previously received data is played out to the atm layer; at which point, it will deactivate itself and be removed from the round-robin. in absence of defects, the s/uni-ima-84 will bring down the link without loss of data. 10.2.5.7 rate changes when the ripp changes the state of a link to active, it programs the appropriate idcc scheduler with the new rate. this is done by providing a vector that identifies the active lids for the group. this vector is used to determine the number of links for the rate calculation and is then passed on to the tima or
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 111 rdat to indicate the lids to include in the round robin. the idcc will only change its rate at ima frame boundaries. 10.2.6 support of ima test pattern procedure s/uni-ima-84 supports the ima test pattern procedure in both the tx direction (ne initiated) and rx direction (fe initiated). in the tx direction, the s/uni-ima-84 updates the tx test control info and tx test pattern field in the outgoing icp cells, as prompted by the relevant update_test_ptn command. meanwhile, the s/uni-ima-84 will always compare the rx test pattern field received in the incoming icp cells with the tx test pattern value being transmitted, and save the result on a per-link basis in the group context memory. in the rx direction, the s/uni-ima-84 always analyzes the tx test control info field in the incoming icp cells. if the test link command field is set to ?active?, the tx test pattern field in the incoming icp cells on the selected link will be copied to the rx test pattern field in the outgoing icp cells. otherwise the rx test pattern field in the outgoing icp cells will be filled with ?0xff?. 10.2.7 support of symmetric/asymmetric operation modes s/uni-ima-84 supports all three possible group symmetry modes: symmetric configuration and symmetric operation; symmetric configuration and asymmetric operation; asymmetric configuration and asymmetric operation. for symmetric configuration, the number of tx and rx links in the group must be the same; for asymmetric configuration, that restriction does not apply. the support for asymmetric/symmetric operation modes is part of the s/uni-ima functionality. the symmetric operation mode is treated as a special case of the asymmetric operation, where the tx and rx lsm on the same physical link are inter-dependent. 10.2.8 support of different ima versions it should be noted that the technique used to report rx information over the link information fields in the icp cells when the group is configured in the symmetrical configuration and operation mode differs in the ima v1.1 implementations and the ima v1.0 implementations.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 112 the details of the differences between ima v1.1 and ima v1.0 can be found in appendix c of the atm forum ima 1.1 specification.. the s/uni-ima-84 is primarily designed to be ima v1.1 compliant. however, it may also be programmed to analyze the incoming icp cells and generate outgoing icp cells using ima v1.0 style, given the group is symmetrically configured. ima v1.0 is not supported for asymmetrical groups. support of ima v1.0 versus ima v1.1 is selectable on a per-group basis. since the rx link state is reported on the tx lid byte, the rx_link state is reported as unusable prior to lid validation unlike in ima 1.1 where it is reported as ?not in group? prior to lid validation. 10.2.9 sdram interface the s/uni-ima-84 uses the external sdram to buffer queued cells. the cell- buffer sdram interface permits a single device, with 4m addressing capability, for a total of 8 mbytes of storage. it has a 16-bit wide data bus, with crc-16 checking applied on a per-cell basis. each cell takes up 64 bytes of memory. the crc-16 is applied to words 0 through 30. if an error occurs, an interrupt is sent to the microprocessor, and the cell is sent to the atm layer anyway. the following diagram shows the cell storage map with the 64-byte memory boundary. figure 21 - cell storage map word # 15 bits 0 write pointer + 0 dcb status[15:0] 1 dcb status[31:16] 2 header1 header2 3 header3 header4 4 reserved 5 status reserved
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 113 6 payload1 payload2 ? ? 28 payload45 payload46 29 payload47 payload48 30 reserved 31 crc-16 the clock source drawn in figure 22 and figure 23 must be completely skew aligned between the s/uni-ima-84 and the sdram clock input pins. the following diagrams illustrate the various configurations supported: figure 22 - 2 mbyte cke clk addr/ctrl dqm dq[15:0] 2 x 2k x 256 x 16 1 clock source sysclk cbcsb cbrasb cbcasb cbweb cbbs[0] cba[11:0] cbdqm cbdq[15:0]
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 114 figure 23 - 8 mbyte sysclk cbcsb cbrasb cbcasb cbweb cbbs[1:0] cba[11:0] cbdqm cbdq[15:0] cke clk addr/ctrl dqm dq[15:0] 4 x 4k x 256 x 16 1 clock source there are three processes, all of which are arbitrated by the sdram arbiter, that access the cell buffer sdram: 1. the rdat, which reads and writes cell and status information. the granularity of access by the rdat is a concatenated 1-cell write, 1-cell read. either the write or the read may not be performed, depending on the rdats requirements. 2. the microprocessor interface, which performs diagnostic reading or writing of 64 bytes of data. this data is aligned with the cell data. this access is allowed only when the sdram is placed in diagnostic mode and is provided both to enable sdram testing and to initialize the sdram. while it is in diagnostic mode, all regular accesses from the rdat are disabled 3. the refresh controller, which has a programmable refresh rate. the sdram interface will perform the initialization sequence for the sdram. this sequence is triggered by the sdram enable bit in the sdram control register. the sequence will program the sdram with a cas latency of 3, sequential access, write burst mode, and a burst length of 8. applications should ensure that sufficient time is provided between sdram power up and when this enable bit is set.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 115 10.3 link fifos in the transmit direction, per link fifos exist to provide an elastic store to ensure proper operation. the number of cells in the fifo at any particular time varies as a function of the cdv introduced by the insertion of stuff cells and icp cells, the effects of the physical link interface, and the smoothing of data from the atm layer for group level cdv. during operation, these fifos are loaded a cell at a time and emptied in a tdm fashion. the link fifos in the transmit direction are to be 8 cells deep. in the receive direction, the link fifos serve as an interface between the tdm domain and the atm cell domain. cells are gathered in the fifo for each link and then burst out to the external memory by the rdat. the link fifos in the receive direction are 2 cells deep. a diagnostic loopback capability is provided to loopback data from the receive link fifos to the transmit link fifo; this will loopback all links when enabled. 10.4 tc layer 10.4.1 tx tc layer (tttc) the tx tc layer (tttc) performs the tc layer functions. these functions consist of optional hec generation, optional payload scrambling, and cell-rate decoupling through physical layer (idle) cell insertion. this function removes data byte by byte from the per-link fifos as required to provide data to the physical layer function. when the physical layer function needs a byte of data, it will request data from the (tttc). the tttc will then read a byte of data from the per-link fifo. if that byte is the first byte of a cell and the logical channel fifo is empty, the tttc will format the next 53 bytes as a physical layer (idle) cell. if the byte is the fifth byte of a cell, the byte is optionally overwritten by the crc-8 calculation over the previous four bytes for that logical channel. the sixth through 53 rd bytes may be scrambled by a x 43 +1 self-synchronous scrambler. note: since the link fifos are cell based, an underrun cannot happen in the middle of a cell.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 116 10.4.2 rx tc layer (rttc) the rx tc (rttc) layer implements hcs cell delineation, payload descrambling, idle cell filtering and header error detection to recover valid atm cells. these functions are performed in accordance with itu-t recommendation i.432.1. cell delineation is the process of framing to atm cell boundaries using the header check sequence (hcs) field found in the atm cell header. the hcs is a crc-8 (x 8 + x 2 + x + 1) calculation over the first 4 octets of the atm cell header. in accordance with itu-t recommendation i.432.1, the coset polynomial x 6 + x 4 + x 2 + 1 is added (modulo 2) to the received hcs octet before comparison with the calculated result. when performing delineation, correct hcs calculations are assumed to indicate cell boundaries. the cell delineation circuitry performs a sequential bit-by-bit hunt for a correct hcs sequence. this state is referred to as the hunt state. when a correct hcs is found, a particular cell boundary is assumed and the presync state is entered. this state verifies that the previously detected hcs pattern was not a false indication. if the hcs pattern was a false indication, then an incorrect hcs should be received within the next delta cells and the delineation state machine falls back to the hunt state. if an incorrect hcs is not found in this presync period, then a transition to the sync state is made, cell delineation is declared, and all non-idle cells with a correct hcs are passed on. in the sync state, synchronization is not relinquished until alpha consecutive incorrect hcs patterns are found. if this happens, a transition is made back to the hunt state. the state diagram of the cell delineation process is shown in figure 24.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 117 figure 24 - cell delineation state diagram the values of alpha and delta determine the robustness of the cell delineation method. alpha determines the robustness against false misalignments due to bit errors. delta determines the robustness against false delineation in the synchronization process. alpha is chosen to be 7 and delta is chosen to be 6. the loss of cell delineation (lcd) alarm is declared after a programmable threshold of incorrect cells occurs while in the hunt state. the threshold is set by the lcd count threshold register. the threshold has a default value of 104, which translates to 28 ms at 1.55 mbps. all idle cells may be filtered out and not passed to the ima sub-layer. they are identified as cells containing all-zero vpi and vci fields and a one in the clp bit. optionally, unassigned cells (like idle cells except clp is a zero) may also be filtered. note that these should not be filtered for ima links.. all cells with an incorrect hcs octet may optionally be dropped. these cells can also be preserved and tagged as errored. preservation of hec errored cells is required for correct operation of ima. failure to preserve the cells will lead to increased numbers of oif violations and data misordering. header correction is not implemented. for ima operation, there are two unique features: the first is optionally passing cells with errored hec; the second results in passing cells during ocd and lcd.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 118 this is to enable the ima to perform a fast recovery from error conditions. an ocd event will result in a loss of ima frame sync to ensure differential delay checking is performed. 10.5 line side physical layer the s/uni-ima-84 must be configured to support one of either the sbi interface or the 32 clock and data interface. 10.5.1 tx clock/data (tcas) the s/uni-ima-84 supports up to 32 2-pin clock/data serial interfaces to interface with standard framers. each link is independent and has its own associated clock. to enable easier support of ctc, a common clock is also supported using the ctsclk pin. the s/uni-ima-84 responds to the active edge of each transmit clock by generating a single bit. when the external framer needs to insert transmission overhead (such as framing bits) into the data stream provided by the s/uni-ima-84, the framer is required to gap the transmit clock provided to the s/uni-ima-84. this will prevent the s/uni-ima-84 from outputting data bits during the overhead bit period(s). the transmit channel assigner block (tcas) processes up to 32 virtual links. data for all links is sourced from a single byte-serial stream from the tc layer. for each link, the tcas provides a holding register. the tcas also performs parallel-to-serial conversion to form a bit-serial stream. when multiple links are in need of data, tcas requests data from upstream blocks on a fixed priority basis with link tsdata[0] having the highest priority and link tsdata[31] the lowest. links containing a t1 or an e1 stream may be channelized. data at each time- slot may be assigned either: (1) to be sourced from the virtual link or (2) to be unassigned. this mechanism of assigning timeslots enables support of fractional links. the link clock should only be active during time-slots 1 to 24 of a t1 stream and inactive during the frame bit. similarly, the clock is only active during time- slots 1 to 31 of an e1 stream and inactive during the framing byte. the first bit of time-slot 1 of a channelized link is identified by noting the absence of the clock and its re-activation. with knowledge of the transmit link and time-slot identity, the tcas performs a table look-up to identify which timeslots are in use. links may also be unchannelized. in that case, all data bytes on that link belong to the virtual link. the tcas performs a table look-up to identify the link to which
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 119 a data byte belongs using only the outgoing link identity, as no time-slots are associated with unchannelized links. the link clock is only active during bit-times containing data to be transmitted; it is inactive during bit-times that are to be ignored by the downstream devices, such as framing and overhead bits. 10.5.2 tx null framer (sdfr84) since data is carried over the sbi bus in a framed format, the atm payload must be mapped into the appropriate t1, e1, or ds3 format. the null framer creates bit streams with the appropriate number of bits without performing the actual framing bit generation or signaling insertion. for t1, a t1 frame is created by adding a bit as a placeholder for the framing bit and the atm data is mapped into the 24 ds0 channels. for e1, placeholders are inserted for channels 0 and 16, which are reserved for signaling, and atm data is mapped into the remaining 30 channels. (channels 1 through 15 and 17 through 31). for ds3, a bit is inserted every 21 nibbles for the frame/sub-frame bits. 10.5.3 insert scaleable bandwidth interconnect (insbi) the insert scaleable bandwidth interconnect block maps up to eighty-four t1(1.544 mbp)s links, sixty-three e1 (2.048 mbps) links, or three ds3 (44.736 mbps) links into the sbi bus. the 1.544 mbps links are t1 framed (channelized) with null framing bits. the 2.048 mbps links are e1 framed (channelized) with null framing bytes. the 44.736 mbps links are also framed ds3 with null framing bits. all links sourced from the s/uni-ima-84 over the sbi bus must be framed prior to transmission. links inserted into the sbi bus are timed from the framer device (e.g. pm8315 temux, pm8316 temux-84). in other words, the insbi always acts as a clock slave. the insbi performs sbi tributary justifications under command from the ajust_req signal.. 10.5.4 extract scaleable bandwidth interconnect (exsbi) the extract scaleable bandwidth interconnect (exsbi)block demaps up to 84 t1 (1.544 mbps) links, 63 e1 (2.048 mbps) links, or up to 3 ds3 (44.736 mbps) links from the sbi bus. the 1.544 mbps links must be t1 framed and channelized. the
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 120 2.048 mbps links must be e1 framed and channelized. the 44.736 mbps must also be framed. all egress links extracted from the sbi bus are timed from the source. within the sbi bus, there are three spes. each spe can either 28 t1s, 21 e1s, or 1 ds3 and all of the links within an spe are of the same type. since the exsbi always acts as a clock slave in this application, the link rates of are derived by the data arrival rate. the s/uni-ima-84 is capable of sinking all data received the sbi bus without generating overflows. 10.5.5 rx deframer (sddf84) since data is transferred over the sbi bus in a framed format and s/uni-ima-84 does not process signaling or check any framing patterns, the framing bits are removed from the t1 and ds3 signals and data is forwarded to the tc function in a byte parallel interface. for t1, the framing bit is removed. for e1, bytes 0 and 16 of the channelized e1 frame are removed since they do not carry valid atm payload. for ds3, one framing bit is removed for every 21 nibbles. 10.5.6 rx clock/data (rcas) the s/uni-ima-84 provides up to 32 2-pin clock/data serial interfaces for interconnecting to t1/e1 framers. each link is independent and has its own associated clock. for each link, the data is sent through a serial to parallel conversion to form data bytes. the data bytes are multiplexed, in byte serial format, for delivery to the tc layer. in the event where multiple streams have accumulated a byte of data, multiplexing is performed on a fixed priority basis, with link #0 having the highest priority and link #31 the lowest. for the clock and data interface, the framer must gap the clock for all framing bits for t1 and for the framing byte for e0. links containing a t1 or an e1 stream may be channelized. for channelized links, the link clock is only active during time-slots 1 to 24 of a t1 stream; it is inactive during the frame bit. similarly, the clock is only active during time-slots 1 to 31 of an e1 stream and inactive during the framing bytes. each time-slot may
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 121 be independently configured to be provisioned (contain valid data) or unprovisioned. the rcas performs a table lookup to assign the provisioned time-slots to a virtual link. after the selected timeslots are grouped into a virtual link, virtual links are referred to as links. this look-up should be used to remove byte 16 of the e1 frame, since byte 16 contains signaling data not atm data and is also used to implement a fractional t1 or e1. the first bit of time-slot 1 of a channelized link is identified by noting the absence of the clock and its re- activation. links may also be unchannelized. in this mode, all data is assumed to be valid atm data. the link clock is only active during bit times containing data to be processed and inactive during bits that are to be ignored by the rcas, such as framing and overhead bits. the rcas provides diagnostic line-side loopback that is selectable on a per- channel basis. when a channel is in diagnostic loopback, data on the received links originally destined for that channel is ignored. transmit data of that channel is substituted in its place. 10.6 microprocessor interface the microprocessor interface block provides the interrupt logic and an interface to normal-mode registers contained within the design blocks. the normal mode registers are required for normal operation. 10.6.1 mapping and link identification within the clock/data interface, the external links are mapped to a contiguous space identified as virtual links. to support multiple fractional tc flows on a single external signal, a mapping is used to split a single channelized external signal into multiple virtual links. at the per-link fifos, the clock/data virtual link naming convention is replaced 1:1 with the physical link naming convention. the s/uni-ima-84 processes 84 physical links, numbered 0 to 83. each line interface uses a different link naming convention, based on the nature of the interface: the sbi interface uses three spes, each carrying 28 tributaries, and the clock and data interface uses 32 external signal pins, which are mapped to 84 virtual links. in both cases, the 84 streams to/from the line interfaces are referred to a physical links elsewhere inside the device.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 122 10.6.1.1 sbi within the sbi interface, the links are identified by the spe and the tributary number within the spe. at the per-link fifos, the spe and tributary number are mapped to a contiguous space identified as physical links 0 through 83. these are referred to as the physical link ids. spe1, tributaries 1 to 28 are mapped to physical links 0-27. spe2, tributaries 1 to 28 are mapped to physical links 28 to 55; and spe3, tributaries 1 to 28 are mapped to physical links 56 to 83. if the spes are in e1 mode, then only the lowest 21 of the 28 possible tributaries are used. if the spes are in ds3 mode, only one link per spe is mapped. in this case, only physical link ids 0, 28, and 56 are used. 10.6.1.2 clock/data within the clock and data interface, the external signals rsclk/tsclk and rsdata/tsdata are identified by sequential numbers from 0 to 31. within the rcas/tcas, these 32 external signals are mapped to a contiguous space identified as virtual links 0 through 83. to support multiple fractional tc flows on a single external signal, rcas/tcas mapping is used to split a single channelized external signal into multiple virtual links. at the per-link fifos, the rcas/tcas virtual link naming convention is replaced 1:1 with the physical link naming convention. 10.6.1.3 ima within the ima sublayer, mapping is performed between the physical link ids and the any-phy/utopia l2 virtual phy address. this mapping can be a one-to-one relationship as for tc connections or it may be a many-to-one relationship as for an ima group. the physical link to virtual phy mapping is independent in the rx and tx directions. the selection of the rx vphy id in any-phy or single port utopia l2 mode is unconstrained as this id exists only as a prepend. in multiple port utopia l2 mode, the rx vphy id must be a unique value between 0 and 30 for each flow. ? the selection of the tx vphy id is limited by the following rule:
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 123 ? all groups must have a unique value between 0 and 83.(0 to 30 for utopia l2 mode). note: the actual address used on the any-phy bus to access a particular channel is a combination of the tx vphy id (bits 6:0) and the tx any-phy address config reg(bits 15:7). 10.6.2 interrupt driven error/status reporting the interrupt logic has several layers. the top layer of the interrupt logic, the master interrupt register, indicates from which block the interrupt came. once the block is determined the processor can access the appropriate block to determine the interrupt cause. 10.6.2.1 line interface interrupts the line interface sources three interrupts: sbi_drop_intr, sbi_add_intr, and sbi_alarm_intr. the sbi_drop_intr indicates there is an interrupt pending related to the sbi-drop bus, also known as the extract sbi bus. the extract master interrupt status register needs to be read to determine the cause of the interrupt. the sbi_add_intr indicates there is an interrupt pending related to the sbi-add bus, also known as the insert sbi bus. the insert master interrupt status register needs to be read to determine the cause of the interrupt. the sbi_alarm_intr indicates that an alarm was detected on a link from the sbi. the sbi alarm interrupt registers will identify which link failed. 10.6.2.2 tc layer interrupts the tc layer sources 4 different interrupts that are reported through a fifo structure. as each interrupt occurs it is placed into a fifo along with a link identifier to uniquely identify the link. the error conditions reported through this structure include hec errors, loss of cell delineation (lcd) state change, out of cell delineation (ocd) state change, and receive link fifo overflow. to determine the actual states of lcd and ocd it is necessary to query the individual link status. if this fifo overflows, it is necessary to query the status of all links in order to retrieve accurate state information. 10.6.2.3 ima interrupts the ima sub-layer sources four interrupts: ripp_intr, tima_intr, rdat_intr, and icp_cell_avl. the ripp_intr indicates that either a status
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 124 change or an error occurred on an ima group. the ripp interrupt status fifo contains the groups that have enabled conditions active. the ripp interrupt status fifo is managed so that each group will only ever have a single entry in the fifo. to facilitate interrupt processing, a ripp command is provided to gather all interrupts and status for a group and all of the links within the group in one snapshot. tima_intr provides information that a link fifo has overflowed. during normal operations, this will only happen when: (1) the tima is misconfigured or (2) the rate difference between the clocks in an ima group is greater than the maximum tolerance. to determine which link has experienced a problem, the tima link fifo overflow status registers should be read. rdat_intr indicates either: (1) that cells were dropped due to any- phy/utopia congestion or (2) that tc group cells were dropped due to fifo overflow. to determine the cause of the interrupt, the rdat master interrupt register should be read. icp_cell_avl indicates that an icp cell is available in the icp cell buffer. to enable diagnostics, the capability to forward a group?s icp cells to the microprocessor is provided. when a cell is forwarded to the microprocessor, it is placed in the icp cell buffer and the interrupt is triggered. as new icp cells arrive, they overwrite the icp cell buffer unless the buffer is locked for reading. once the icp cell buffer is locked, further icp cells will not be forwarded until the icp cell buffer is unlocked. this trace can be enabled on a per-group basis. 10.6.2.4 miscellaneous interrupts misc_intr indicates that an interrupt condition exists in the miscellaneous interrupt register. these bits are read-and-clear and usually indicate that transitory conditions have occurred, such as parity errors, sdram crc errors, interrupt fifo overflows, and utopia l2 interface errors. 10.6.3 registers the register memory map in table 4 shows where the normal mode registers are accessed. the resulting register organization is split into sections: master configuration registers, tc layer, sbi interface, clock/data interface and ima sublayer registers. on power up, the s/uni-ima-84 requires configuration. for proper operation, register configuration is necessary in order to program addresses for the any-
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 125 phy ports, enable the sdram, configure the line interface and chose ima or tc mode for each link/group. by default, interrupts will not be enabled. the line-side-access defaults to a disabled state; this results in all line side output pins being tristated. when the line mode is chosen, sbi, or clock/data, the pins will be enabled. table 4 register memory map address register 0x000 ? 0x05e master configuration and interrupts 0x000 global reset 0x002 global configuration 0x004 jtag id (msb) 0x006 jtag id (lsb) 0x008 master interrupt register 0x00a miscellaneous interrupt register 0x00c rttc interrupt fifo 0x00e reserved 0x010 master interrupt enable register 0x012 miscellaneous interrupt enable register 0x014 tc interrupt enable register 0x016- 0x01e reserved 0x020 transmit any-phy/utopia cell available enable 0x022 receive utopia cell available enable 0x024 receive any-phy/utopia config register (rxaps_cfg) 0x026 transmit any-phy/utopia config register (txaps_cfg) 0x028 transmit any-phy address config register (txaps_add_cfg)
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 126 address register 0x02a- 0x03e reserved 0x040 sdram configuration 0x042 sdram diagnostics 0x044 sdram diag burst ram indirect access 0x046 sdram diag indirect burst ram data lsb 0x048 sdram diag indirect burst ram data msb 0x04a sdram diag write cmd 1 0x04c sdram diag write cmd 2 0x04e sdram diag read cmd 1 0x050 sdram diag read cmd 2 0x052- 0x05e reserved 0x060- 0x07e tc layer 0x060 tttc indirect link control register 0x062 tttc indirect link configuration register 0x064- 0x06e tttc reserved 0x070 rttc indirect link control register 0x072 rttc indirect link configuration register 0x074 rttc indirect link interrupt and status register 0x076 rttc indirect link hcs error count register 0x078 lcd count threshold 0x07a- 0x07e reserved 0x080- 0x0fe sbi interface 0x080 sbi bus configuration
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 127 address register 0x082 reserved 0x084- 0x08e sbi extract bus alarm interrupt registers 0x090- 0x09a sbi extract bus alarm status registers 0x09c- 0x09e sbi reserved 0x0a0 sbi extract control register 0x0a2 sbi extract fifo underrun interrupt status register 0x0a4 sbi extract fifo overrun interrupt status register 0x0a6 sbi extract tributary ram indirect access address register 0x0a8 sbi extract tributary ram indirect access control register 0x0aa reserved 0x0ac sbi extract tributary control ram indirect access data register 0x0ae sbi extract parity error interrupt reason register 0x0b0- 0x0ba reserved 0x0bc sbi extract depth check interrupt status register 0x0be sbi extract master interrupt status register 0x0c0 sbi insert control register 0x0c2 sbi insert fifo underrun interrupt status register 0x0c4 sbi insert fifo overrun interrupt status register 0x0c6 sbi insert tributary register indirect access address register 0x0c8 sbi insert tributary register indirect access control register 0x0ca reserved
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 128 address register 0x0cc sbi insert tributary control indirect access data register 0x0ce- 0x0e0 reserved 0x0e2 sbi insert depth check reset interrupt status register 0x0e4 sbi insert master interrupt status register 0x0e6- 0x0fe reserved 0x100- 0x1fe clock/data interface 0x100 rcas indirect link and time-slot select 0x102 rcas indirect channel data 0x104 rcas framing bit threshold 0x106 rcas channel disable 0x108 ? 0x13e rcas reserved 0x140 ? 0x17e rcas link #0 to link #31 configuration 0x180 tcas indirect link and time-slot select 0x182 tcas indirect channel data 0x184 tcas framing bit threshold 0x186 tcas idle time-slot fill data 0x188 tcas channel disable register 0x18a ? 0x1be tcas reserved 0x1c0 ? 0x1fe tcas link #0 to link #31 configuration 0x200- 0x3fe ima sublayer 0x200 ripp control
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 129 address register 0x202 ripp indirect memory access control 0x204- 0x206 ripp indirect memory data register array 0x208 delay configuration register 0x20c ripp timer tick configuration register 0x20e group timeout register #1 0x210 group timeout register #2 0x212 tx link timeout register 0x214 rx link timeout register 0x216 ripp interrupt status register 0x218 ripp group interrupt enable register 0x21a ripp tx link interrupt enable register 0x21c ripp rx link interrupt enable register 0x220- 0x22c ripp command register 0x22e command read data control register 0x230 icp cell forwarding status register 0x232 icp cell forwarding control register 0x240- 0x29e ripp command data register array 0x2c0- 0x2de forwarding icp cell buffer 0x300 rdat indirect memory command 0x302 rdat indirect memory address 0x304 rdat indirect memory data lsb 0x306 rdat indirect memory data msb 0x308 rdat configuration 0x30a receive atm congestion status lsb
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 130 address register 0x30c receive atm congestion status msb 0x30e receive tc overrun status 0x310 rdat master interrupt status 0x312 receive atm congestion interrupt enable lsb 0x314 receive atm congestion interrupt enable msb 0x316 rdat master interrupt enable 0x318- 0x31e reserved 0x320 tima indirect memory command 0x322 tima indirect memory address 0x324 tima indirect memory data lsb 0x326 tima indirect memory data msb 0x328- 0x332 tx link fifo overflow status 0x340 txidcc indirect link access 0x342 txidcc indirect link data register #1 0x344- 0x34e reserved 0x350 rxidcc indirect link access 0x352 rxidcc indirect link data register #1 0x354- 0x364 reserved 0x366 dll control status 0x368- 0x3ff reserved for all register accesses, csb must be low.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 131 11 normal mode register description normal mode registers are used to configure and monitor the operation of the s/uni-ima-84. normal mode registers (as opposed to test mode registers) are selected when a[10] is low. notes on normal mode register bits: 1. writing values into unused register bits has no effect. however, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic zero. reading back unused bits can produce either a logic one or a logic zero; hence, unused register bits should be masked off by software when read. 2. all configuration bits that can be written into can also be read back. this allows the processor controlling the s/uni-ima-84 to determine the programming state of the block. 3. writeable normal mode register bits are cleared to logic zero upon reset unless otherwise noted. 4. writing into read-only normal mode register bit locations does not affect s/uni-ima- 84 operation unless otherwise noted. 5. certain register bits are reserved. these bits are associated with megacell functions that are unused in this application. to ensure that the s/uni-ima-84 operates as intended, reserved-register bits must only be written with logic zero. similarly, writing to reserved registers should be avoided.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 132 11.1 global registers register 0x000: global reset bit type function default 15 r/w reset 1 14 ro bist_done x 13:7 unused 0 6:4 ro type[2:0] 001 3:0 ro id[3:0] 0 id[3:0]: the id bits can be read to provide a binary number indicating the s/uni-ima- 84 feature version. these bits are incremented only if features are added in a revision of the chip. type[2:0]: the type bits can be read to distinguish the s/uni-ima-84 from the other members of the s/uni-ima-84 family of devices. the s/uni-ima-84 is identified by a value of ?001?. bist_done the bist_done indicates when the internal ram initialization is complete. once the ram initialization is complete, the internal rams may be accessed. prior to bist_done transitioning to a ?1?, any internal ram accesses are ignored. reset: the reset bit implements a software reset for the entire s/uni-ima-84. if the reset bit is a logic 1, the entire s/uni-ima-84 is held in reset except for the microprocessor interface. while in reset, the only register that is accessible is the global reset register. this bit is not self-clearing; therefore, a logic 0 must be written to bring the s/uni-ima-84 out of reset. holding the s/uni-ima-84 in a reset state effectively puts it into a low power, stand-by mode. a hardware reset sets the reset bit, thus asserting the software reset.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 133 register 0x002: global configuration bit type function default 15:8 unused 0 7 r/w chan_cd 0 6 r/w max_dcb_dept h 0 5 r/w ctsclk_sel 0 4 r/w line_en 0 3 r/w line_loop 0 2 r/w u2u_loop 0 1:0 r/w line_mode[1:0] 0 line_mode[1:0] enables the selected line interface mode. 00) disabled (all line interface signals are tristated.) 01) sbi mode 10) clock/data mode 11) reserved u2u_loop when set, all cells received by the any-phy/utopia interface are sent back out to the any-phy/utopia (regardless of single- or multi-addressing mode). for proper operation, if the receive interface is in multi address utopia mode, the transmit interface must also be in utopia mode. 0) any-phy/utopia in normal mode 1) any-phy/utopia in remote loopback mode line_loop when set, all cells received by the sbi or clock/data interfaces are sent back out to the sbi or clock/data 0) line side in normal mode 1) line side remote loopback mode
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 134 line_en when line_en is set, line side traffic flow is enabled. this configuration bit should be written to a one after the line_mode has been configured and prior to normal operation. ctsclk_sel when ctsclk_sel is set and line_mode=?10?, the ctsclk pin is used as the clock for all transmit serial line clocks. when ctsclk_sel is not set and line_mode=?10?, the tsclk[31:0] pins are used for all transmit serial line clocks when line_mode=01, ctsclk_sel is ignored. max_dcb_depth: this indicates the number of cells that can be stored for a single link in the external sdram. this determines the number of bits the rdat will use for the read and write pointers. to ensure correct operation, the user must ensure that the proper amount of sdram is available. see figure 10 for details. 0) 256 cells per link 1) 1024 cells per link chan_cd: this indicates that the channelized cell delineation may be used. channelized cell delineation results in faster cell delineation since an octet by octet search is performed instead of a bit by bit search. a nibble by nibble search is performed if the spe is in ds3 mode. this option may only be used when operating with a channelized interface such as the sbi interface or the clk/data interface in channelized mode. if any links are operating in unchannelized mode, this bit may not be set. 0) use bit by bit search for cell delineation. (safe mode) 1) use octet or nibble search for cell delineation (only should be set if operating with channelized line interface for all links
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 135 register 0x004: jtag id (msb) bit type function default 15:0 ro jtagid(31:16) 0x0734 jtagid[31:16]: the jtag id register (jtagid[31:16]) of the s/uni-ima-84 device. the jtag id is the same as the one read by the jtag port.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 136 register 0x006: jtag id (lsb) bit type function default 15:0 ro jtagid(15:0) 0x10cd jtagid[15:0]: the jtag id register (jtagid[15:0]) of the s/uni-ima-84 device. the jtag id is the same as the one read by the jtag port.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 137 11.2 master interrupt registers register 0x008: master interrupt register bit type function default 15:9 ro unused 0 8rotc_intr 0 7 ro misc_int 0 6 ro sbi_alarm 0 5 ro sbi_drop_intr 0 4 ro sbi_add_intr 0 3 ro icp_cell_avl 0 2 ro rdat_intr 0 1 ro tima_intr 0 0 ro ripp_intr 0 this register is the top of the interrupt tree. it indicates which lower level interrupt registers have interrupts pending. note that the respective bits will remain set as long as the underlying condition remains active. ripp_intr when set, there is an interrupt pending from the ripp block. read the ripp_intr_fifo located in register 0x216 to determine the group which caused the interrupt. this bit indicates current status and will clear only when ripp_intr_fifo is empty. on read: 0) no interrupt pending from the ripp block. 1) interrupt pending from the ripp block. tima_intr when set, there is an interrupt pending from the tima block. read the tima_overflow_regs located in registers 0x328-0x332 to determine the cause of the interrupt. this bit indicates current status and will clear only when no interrupt conditions remain in tima_overflow_reg. on read: 0) no interrupt pending from the tima block. 1) interrupt pending from the tima block.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 138 rdat_intr when set, there is an interrupt pending from the rdat block. read the rdat_intr_status_reg located in register 0x310 to determine the cause of the interrupt. this bit indicates current status and will clear only when no interrupt conditions remain in rdat_intr_status_reg. on read: 0) no interrupt pending from the rdat block. 1) interrupt pending from the rdat block. icp_cell_avl when set, it indicates that a new icp cell is available in the icp cell buffer. the icp cell buffer can be used to extract icp cells for a group. this bit is cleared when register 0x230 icp cell forwarding status is read. 0) no icp cell is available. 1) an icp cell is available in the icp buffer. sbi_add_intr when set, it indicates that an interrupt is pending related to the sbi-add bus (also known as the insert sbi bus). read the insert master interrupt status register (register ?0x0e4?) to find the cause of the interrupt. this bit indicates current status and will clear only when no interrupt conditions remain in the insert master interrupt status register. on read: 0) no sbi add bus interrupt pending. 1) sbi add bus interrupt is pending. sbi_drop_intr when set, it indicates that an interrupt is pending related to the sbi-drop bus, also known as the extract sbi bus. read the extract master interrupt status register (register 0x0be) to find the cause of the interrupt. this bit indicates current status and will clear only when no interrupt conditions remain in the extract master interrupt status register. on read: 0) no sbi drop bus interrupt pending 1) sbi drop bus interrupt is pending sbi_alarm when set, it indicates that an interrupt is pending in one of the 0x084-0x08e: sbi extract alarm interrupt registers located at 0x084-0x08e. registers. this bit indicates current status, and will clear only when no interrupt conditions exist in either sbi alarm registers. on read: 0) no sbi alarm pending 1) sbi alarm pending
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 139 misc_intr when set, it indicates that an interrupt is pending in the miscellaneous interrupt register located in register 0x00a. this bit indicates current status, and will clear only when no interrupt conditions exist in the miscellaneous interrupt register. on read: 0) no miscellaneous interrupt pending 1) miscellaneous interrupt pending tc_intr when set, indicates that a tc layer is pending in the tc_intr_fifo. this bit indicates current status and will clear only when the tc_intr_fifo is empty. 0) no tc interrupts in the tc_intr fifo. 1) tc interrupts are present in the tc_intr_fifo.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 140 register 0x00a: miscellaneous interrupt register bit type function default 15:5 r2c reserved 0 4 r2c tc_intr_fovr_er r 0 3 r2c sdram_crc_err 0 2 r2c tx_utop_cellxfe rr 0 1 r2c tx_utop_par_er r 0 0 r2c rx_utop_xfr_er r 0 this register collects the miscellaneous interrupts. these interrupt bits are cleared on read. if any bit in this register is set and is enabled, the misc_int bit will be set in the master interrupt register. rx_utop_xfr_err when set, it indicates that the receive any-phy/utopia interface was requested to send a cell when it did not have one available. this condition is a protocol error in the receive any-phy/utopia bus. this bit is cleared on read. 0) no protocol error occurred. 1) the rx any-phy/utopia interface was requested to send a cell when a cell was not available. tx_utop_par_err when set, it indicates that the transmit any-phy/utopia interface experienced a parity error. this bit is cleared on read. 0) no parity error occurred on the tx any-phy/utopia interface. 1) a parity error occurred on the tx any-phy/utopia interface.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 141 tx_utop_cellxferr when set, it indicates that the transmit any-phy/utopia interface experienced an unexpected start of cell in the middle of a cell transfer. this bit is cleared on read. 0) no cell transfer error occurred on the tx any-phy/utopia interface. 1) a cell transfer error occurred on the tx any-phy/utopia interface. sdram_crc_err when set, it indicates that a sdram crc error occurred when a cell buffer was read from sdram. this bit is cleared on read. 0) no sdram crc error occurred. 1) sdram crc error occurred. tc_intr_fovr_err when set, it indicates that the rttc interrupt fifo overflowed and status reporting information was lost. to determine the status of the physical links, the physical-link status for each link must be polled. this bit is cleared on read. 0) the rttc interrupt fifo has not overflowed. 1) the rttc interrupt fiof has overflowed.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 142 register 0x00c: receive tc interrupt fifo bit type function default 15 ro fifo_busy 0 14 ro fifo_not_empty 0 13:11 ro unused 0 10:4 ro link_id x 3 ro hcs_err x 2 ro lcd_err x 1rofovr_err x 0 ro oocd_err x oocd_err when set, it indicates that an ocd error occurred on the link indicated by link id. this bit is valid only when fifo_not_empty is set and fifo_busy is not set. 0) no ocde error occurred on the link identified by link id. 1) ocde error occurred on the link identified by link id. fovr_err when set, it indicates that the rttc link fifo overflowed on link link_id. this bit is valid only when fifo_not_empty is set and fifo_busy is not set. 0) rttc link fifo did not overflow on the link identified by link_id. 1) rttc link fifo overflowed on the link identified by link_id. lcd_err when set, it indicates that a loss of cell delineation error occurred on the link identified by link id. this bit is valid only when fifo_not_empty is set and fifo_busy is not set. 0) no lcde error occurred on the link identified by link id. 1) lcde error occurred on the link identified by link id.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 143 hcs_err when set, it indicates that a header check sequence error occurred on the link identified by link id. this bit is valid only when fifo_not_empty is set and fifo_busy is not set. 0) no hcse error occurred on the link identified by link id. 1) hcse error occurred on the link identified by link id. link_id[6:0] indicates the physical-link number associated with the error. if in sbi mode, this is in the spe/link format while in clk/data mode this field indicates the link number (0 to 83). this field is valid only when fifo_not_empty is set and fifo_busy is not set. fifo_not_empty indicates that the fifo is not empty and that the data read is valid. this bit is valid only when fifo_busy is not set. 0) fifo empty, data is not valid 1) fifo not empty, data is valid. fifo_busy indicates that the fifo is in the process of retrieving the next entry. the busy bit will generally be cleared within 4 sysclk cycles from the previous read of this field. while this bit is set, the other contents of this register are invalid.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 144 register 0x010: master interrupt enable register bit type function default 15:5 r/w reserved 0 8r/wtc_intr_en 0 7 r/w misc_intr_en 0 6 r/w sbi_alarm_en 0 5 r/w sbi_drop_intr_en 0 4 r/w sbi_add_intr_en 0 3 r/w icp_cell_avl_en 0 2 r/w rdat_intr_en 0 1r/wtima_intr_en0 0 r/w ripp_intr_en 0 the above enable-bits control the corresponding interrupt bits in the master interrupt register. when an enable-bit is set to a logic 1, the corresponding error event will cause intb to go active.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 145 register 0x012: miscellaneous interrupt enable register bit type function default 15:5 ro unused 0 4 r/w tc_intr_fovr_er r_en 0 3 r/w sdram_crc_err_ en 0 2r/wtx_utop_cellxfe rr_en 0 1 r/w tx_utop_par_err en 0 0 r/w rx_utop_xfr_err _en 0 the above enable-bits control the corresponding interrupt bits in the miscellaneous interrupt register. when an enable-bit is set to a logic 1, the corresponding error event will cause the misc_int bit to be set in the master interrupt register.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 146 register 0x014: tc interrupt enable register bit type function default 15:4 ro unused 0 3 r/w hcs_err_en 0 2 r/w lcd_err_en 0 1 r/w fovr_err_en 0 0 r\w oocd_err_en 0 the above enable-bits provide a global enable for the corresponding interrupt bits in the rttc interrupt fifo. if an enable-bit is not set, the corresponding error event will not cause an entry to be written into the tc_intr fifo. when an enable-bit is set to a logic 1, the corresponding error event, if enabled for the link, will cause an entry to be written into the tc intr fifo.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 147 11.3 utopia interface registers these registers control the configuration of the utopia interface. register 0x020: transmit any-phy/utopia cell available enable bit type function default 15:11 r unused 0 10:0 r/w tcaen[10:0] 0 tcaen[10:0]: the tcaen[10:0] bits control the response to polling on the any- phy/utopia transmit port. the tcaen[10:0] bits can be used to enable virtual phys. virtual phys are enabled in groups of eight consecutive addresses; for example, setting tcaen[0] enables addresses 0 through 7, setting tcaen[9] enables addresses 72 through 79, and setting tcaen[10] enables addresses 80 through 83. if a disabled phy address is polled, tca remains high impedance. similarly, phy selection is ignored and no cell is transferred to the s/uni-ima-84 when a disabled phy is addressed. this is typically used to allow more than one slave device to share the transmit utopia bus or to preserve addresses on the any-phy bus. disabling all traffic to the any-phy/utopia input port is achieved by setting all tcaen[10:0] bits to logic 0.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 148 register 0x022: receive utopia cell available enable bit type function default 15:4 unused 0 3:0 r/w rcaen[3:0] 0 rcaen[3:0]: the rcaen[3:0] bits control the response to polling on the receive utopia port when in utopia level 2 multi-address mode. the rcaen[3:0] bits can be used to enable logical channels. logical channels are enabled in groups of eight consecutive addresses; for example, setting rcaen[0] enables addresses 0 through 7 and setting rcaen[3] enables addresses 24 through 30. s/uni-ima-84 drives the rca output signal either high or low, when polled with an address corresponding to a set rcaen bit, depending on the group fifo status. if a disabled phy address is polled, rca remains high impedance. similarly, phy selection is ignored and no cell is transferred from the s/uni-ima-84 when a disabled phy is addressed. this is typically used to allow more than one slave device to share the receive utopia bus. disabling all traffic to the utopia input port while in multi-phy mode is achieved by setting all rcaen[3:0] bits to logic 0. this field is ignored when in any-phy or single port utopia mode.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 149 register 0x024: receive any-phy/utopia config reg (rxaps_cfg) bit type function default 15 r/w ra_enable 0 14:13 r unused 0 12:8 r/w ra_devid[4:0] 0 7:6 r unused 0 5 r/w ra_hecudf 0 4 r/w ra_prepend 0 3 r/w ra_16_bit_mod e 0 2 r/w ra_even_par 0 1 r/w ra_any-phy_en 0 0r/w ra_utop_mod e 0 this register controls the receive side configuration of the any-phy/utopia interface ra_utop_mode selects the operating mode for the receive-side interface. this bit is ignored when any-phy_en is set: 0) utopia-2 single address slave with address prepend. 1) utopia-2 multi-address slave. ra_any-phy_en enables any-phy mode for receive side interface. 0) utopia mode. (use ra_utop_mode for utopia type). 1) any-phy mode. ra_even_par determines the generated parity across data bytes/words sourced by the receive interface. 0) odd parity. 1) even parity.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 150 ra_16_bit_mode when set, the any-phy/utopia receive side interface operates in 16-bit mode. 0) 8-bit mode. 1) 16-bit mode. ra_prepend when set, two bytes are prepended to cells on the any-phy/utopia bus. this prepend is always zero. this prepend is independent of the address prepend used for any-phy mode. 0) no additional bytes are prepended to the cells. 1) two additional bytes are prepended to the cells. ra_hecudf this bit is only valid in single address utopia mode. 0) place the virtual phy id in a prepend. 1) place the virtual phy id in the hecudf. ra_devid[4:0] this field provides the device id that is used for polling and selection in the any-phy mode or in the single address utopia mode. when the address presented on the any-phy/utopia radr interface pins matches this address, the s/uni-ima-84 will respond to polls. the s/uni-ima-84 is selected for a cell transfer when the address on radr at the last cycle that renb is high matches ra_devid. ra_enable enables the receive any-phy/utopia interface. prior to this bit being set, all outputs are tristated and all inputs are ignored on the interface.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 151 register 0x026: transmit any-phy/utopia config reg (txaps_cfg) bit type function default 15 r/w ta_enable 0 14:5 r unused 0 4 r/w ta_prepend 0 3 r/w ta_16_bit_mod e 0 2 r/w ta_even_par 0 1 r/w ta_any-phy_en 0 0 r/w unused 0 this register controls the transmit-side configuration of the any-phy/utopia interface ta_any-phy_en enables any-phy mode for the transmit side interface: 0) utopia-2 multi-address slave 1) any-phy mode. ta_even_par determines the checked parity across data bytes/words received by the any- phy/utopia transmit interface. 0) odd parity 1) even parity. ta_16_bit_mode when set, the tx any-phy/utopia interface operates in 16-bit mode. 0) 8-bit mode 1) 16-bit mode ta_prepend: when set, a single 2-byte prepend is expected on the any-phy/utopia transmit interface. this prepend is independent of the address prepend used for any-phy mode. the prepend is ignored, but the capability is provided to enhance interoperability.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 152 0) no two-byte prepend is expected. 1) two-byte prepend is expected. ta_enable enables the transmit any-phy/utopia interface. prior to this bit being set, all outputs are tristated and all inputs are ignored on the interface.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 153 register 0x028: transmit any-phy address config register (txaps_add_cfg) bit type function default 15:7 r/w cfg_addr_msb 0 6:0 r/w unused 0 cfg_addr_msb(15:7) these bits contain the configured slave address used for any-phy operation in the transmit direction. depending on the mode of the any-phy/utopia interface different bits of this field are used. in any-phy 16-bit mode, the upper nine bits of the prepended address on the any-phy bus is compared with cfg_addr_msb to select the device. the lower seven bits of the prepended address on the any-phy bus are not compared with this field, and are used only to route each cell to the targeted virtual phy fifo. in any-phy 8-bit mode, the msb of the prepended address on the any-phy bus is compared with cfg_addr_msb[7] to select the device. the lower seven bits of the prepended address on the any-phy bus are not compared with this field, and are used only to route each cell to the targeted virtual phy fifo.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 154 in utopia level 2 mode, this register is not used. to disable utopia transmit ports, the transmit any-phy/utopia cell-available enable register
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 155
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 156 11.4 sdram registers register 0x040: sdram configuration bit type function default 15:12 unused 0 11:1 r/w ref_rate [10:0] 0 0 r/w sdram_en 0 this register configures and enables the sdram interface. sdram_en the sdram_en enables the sdram interface. a transition from 0 to 1 starts the sdram self-initialization procedure. this procedure takes 70 sysclk cycles to complete. note that no other sdram accesses are allowed during this period. sdram_en is provided to ensure that the power-up of the sdram is completed before the sdram self-initialization sequence is started. the power-up time is controlled by sdram_en. typically, this must be at least 200 us. when sdram_en = ?0?, no sdram accesses will occur and the chip will not operate properly. 0) sdram accesses are disabled 1) sdram accesses are enabled ref_rate[10:0] defines the sysclk divide-down factor to determine the sdram refresh rate. the ref_rate must be configured prior to setting the sdram_en. a zero value will effectively disable refresh. for example, if the sdram requires 4k refreshes in 64 ms with a sysclk of 50 mhz, the ref_rate should be programmed to: () d x ms mhz period time refresh of clk sys rate ref 30 0 781 64 4096 50 ) _ ( ) _ _ (# _ _ = = = =
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 157 register 0x042 sdram diagnostics bit type function default 15:1 n/a unused 0 0r/w diag_mode0 diag_mode the sdram diagnostic mode (diag_mode) allows the microprocessor to access the sdram for testing and initialization. while in diagnostic mode, the normal sdram accesses are inhibited and the s/uni-ima-84 will not operate properly. 0) diagnostic access is disabled and the s/uni-ima-84 operates normally. 1) diagnostic access is enabled. the sdram may be accessed via indirect access as described in section 11.4 using registers 0x44-0x50.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 158 register 0x044: sdram diag burst ram indirect access bit type function default 15 ro br_busy 0 14:5 n/a unused n/a 4:0 r/w br_addr[4:0] 0 writing to this register triggers either a write to the burst write ram or a read from the burst read ram. see 12.6.1 for further details. br_addr [4:0]: the burst-ram address (br_addr [4:0]) indicates the ram address to be configured or interrogated. the burst ram is divided into 2 segments: the first is burst write ram, which is used to store data to be loaded into the external sdram; the second is the burst read ram, which is used to collect data read from the external sdram. the access to the burst-write ram is always a write operation while the access to the burst-read ram is always a read operation. see figure 25 for the format of the burst ram. ? 0x00-0x0f: burst-write ram ? 0x10-0x1f: burst-read ram br_busy: the indirect access command bit (br_busy) reports the progress of an indirect access. br_busy is set high when the register is written to trigger an indirect access; it will stay high until the access is complete. once the access is complete, the br_busy signal is reset. this register should be polled: (1) to determine when data from an indirect read operation is available in the sdram indirect burst ram data register or (2) to determine when a new indirect write operation may commence.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 159 register 0x046: sdram diag indirect burst ram data lsb bit type function default 15:0 r/w br_data_lsb 0 this register should not be written while the br_busy bit is set in the sdram burst ram indirect access register. br_data_lsb: the br_data_lsb represents either: (1) the least significant 16 bits of the data to be written to internal memory or (2) the least significant 16 bits of the read data resulting from the previous read operation. the read data is not valid until after the br_busy bit has been cleared.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 160 register 0x048: sdram diag indirect burst ram data msb bit type function default 15:0 r/w br_data_msb 0 this register should not be written while the br_busy bit is set in the sdram burst ram indirect access register. br_data_msb: the br_data_msb represents either: (1) the most significant 16 bits of the data to be written to internal memory or (2) the most significant 16 bits of the read data resulting from the previous read operation. the read data is not valid until after the br_busy bit has been cleared. the following explains the burst ram accessed by the indirect access. burst ram: the microprocessor has access to the external sdram for testing and initialization. there is a 64-byte cell buffer for writing to the external sdram and a 64-byte cell buffer for storing data read from the external sdram. figure 25 shows the format of the cell in the burst ram.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 161 figure 25 -burst ram format word # 31 bits 0 0x00 burst write (0) 0x01 burst write (1) ? ? 0x0f burst write(15) 0x10 burst read (0) 0x11 burst read (1) ? ? 0x1f burst read(15)
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 162 register 0x04a: sdram diag write cmd 1 bit type function default 15:0 r/w wr_buffer_addr[15:0] 0 wr_buffer_addr[15:0] indicates the lower 16 bits of the addresses of the cell buffer to write. sdram diag write cmd 2 provides the upper address bit and triggers the burst access to happen.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 163 register 0x04c: sdram diag write cmd 2 bit type function default 15 r wrbusy 0 14:1 unused 0 r/w wr_buffer_addr[16] 0 a write to the sdram diag wr_cmd 2 register will trigger a transfer of data from the write burst ram to the external sdram. the lower bits of the address of the cell buffer in the external sdram are given in the sdram diag write cmd 1 register. wr_buffer_addr[16] indicates the upper bit of the addresses of the cell buffer to write. sdram diag write cmd 1 provides the lower address bits. wrbusy the write busy bit (wrbusy) reports the progress of the write access to sdram. wrbusy is set high when this register is written; this triggers the sdram access; it stays high until the access is complete. at which point, wrbusy will be set low. this register should be polled to determine when a new diagnostic write operation may commence. while the wrbusy bit is set, no indirect accesses to the write burst ram should be performed.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 164 register 0x04e: sdram diag read cmd 1 bit type function default 15:0 r/w rd_buffer addr[15:0] 0 rd_buffer_addr[15:0] indicates the lower 16 bits of the addresses of the cell buffer to read. sdram diag read cmd 2 provides the upper address bit and triggers the burst access to happen.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 165 register 0x050: sdram diag read cmd 2 bit type function default 15 r rdbusy 0 14:1 unused 0 r/w rd_buffer addr[16] a write to the sdram diag read cmd 2 register will trigger a transfer of data from the external sdram to the read burst ram. the lower bits of the address of the cell buffer in the external sdram are given in the sdram diag read cmd 1 register. rd_buffer_addr[16] indicates the upper bit of the addresses of the cell buffer to read. sdram diag read cmd 1 provides the lower address bits. rdbusy the read busy bit (rdbusy) reports the progress of the read access to sdram. rdbusy is set high when this register is written; this triggers the sdram access; it stays high until the access is complete. at which point, rd_busy will be set low. this register should be polled to determine when the data is available in the burst ram.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 166 11.5 tc layer registers register 0x060: tttc indirect link control register bit type function default 15 r lbusy 0 14 r/w lrwb 0 13:7 unused 0 6:5 r/w spe[1:0] 0 4:0 r/w link[4:0] 0 this register provides the link number used to access the tttc link provision ram. writing to this register triggers an indirect link register access. link[4:0],spe[1:0]: link[4:0] and spe[1:0] are used to specify the link to be configured or interrogated in the indirect link access. sbi mode: valid values for spe are 0x1 to 0x3, and valid values for link are 0x1 to 0x1c. clk/data mode: spe and link are combined to form the virtual link number. 84 virtual links are available. valid values for the spe/link fields are 0x00 to 0x53. lrwb: the link indirect access control bit (lrwb) selects between either a configure (write) or interrogate (read) access to the link-context ram. writing a logic 0 to lrwb triggers an indirect write operation. data to be written is taken from the indirect link data registers. writing a logic 1 to lrwb triggers an indirect read operation. the read data can be found in the indirect link data registers. lbusy: the indirect link access status bit (lbusy) reports the progress of an indirect access a write to the indirect link address register triggers an indirect access and sets lbusy to logic 1; it will remain logic 1 until the access is complete. this register should be polled to determine either: (1) when data from an indirect read operation is available in the indirect link data registers or (2)
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 167 when a new indirect write operation may commence. the lbusy is not expected to remain at logic 1 for more than 86 refclk cycles.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 168 register 0x062: tttc indirect link configuration register bit type function default 15:3 unused 0 2 r/w dhcs 0 1 r/w reserved 0 0 r/w dscr 0 this register contains either: (1) data read from the tttc link provision ram after an indirect link read operation or (2) data to be inserted into the tttc link provision ram in an indirect link write operation. dscr: the indirect scrambling disable bit (dscr) configures scrambling. the scramble disable bit to be written to the link provision ram, in an indirect link write operation, must be set up in this register before triggering the write. when dscr is logic 1, scrambling is disabled. when dscr is logic 0, the 48 byte payload is scrambled. dscr reflects the value written until the completion of a subsequent indirect link-read operation. dhcs: the disable hcs (header check sequence) bit (dhcs) configures the insertion of the hcs in the fifth byte of the cell. the value of dhcs to be written to the link provision ram, in an indirect link write operation, must be set up in this register before triggering the write. when dhcs is logic 0, the crc-8 calculation over the first four bytes of the cell overwrites the fifth byte. when dhcs is logic 1, the fifth byte of the cell passes through unmodified. dhcs reflects the value written until the completion of a subsequent indirect link-read operation.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 169 register 0x070: rttc indirect link control register bit type function default 15 r lbusy 0 14 r/w lrwb 0 13 r/w drhcse 0 12:7 unused 0 6:5 r/w spe[1:0] 0 4:0 r/w link[4:0] 0 this register provides the link number used to access the rttc link provision ram. writing to this register triggers an indirect link-register access. link[4:0],spe[1:0]: link[4:0] and spe[1:0] are used to specify the link to be configured or interrogated in the indirect link access. sbi mode: valid values for spe are 0x1 to 0x3, and valid values for link are 0x1 to 0x1c. clk/data mode: spe and link are combined to form the virtual link number. 84 virtual links are available. valid values for the spe/link fields are 0x00 to 0x53. drhcse: disable reset of the hcs error count (drhcse) disables automatic reset of the hcs error counter (hcserr). when the bit is set to logic 0, automatic reset of the hcs error counter is enabled. if an indirect read is initiated (i.e., crwbs written with logic 1) with drhcse logic 0, the hcs error counter is reset to zero upon completion of the indirect read. when the drhcse bit is set to logic 1, automatic reset of the hcs error counter is disabled. an indirect read results in the interrupt status, as well as the hcserr count, being read (and possibly cleared). in this situation, the drhcse bit is useful for separating interrupt processing from hcserr count accumulation because it can disable the hcserr count reset when querying for interrupts.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 170 lrwb: the link indirect access control bit (lrwb) selects between a configure (write) or interrogate (read) access to the link context ram. writing a logic 0 to lrwb triggers an indirect write operation. data to be written is taken from the indirect link data registers. writing a logic 1 to lrwb triggers an indirect read operation. the read data can be found in the indirect link data registers. lbusy: the indirect access status bit (lbusy) reports the progress of an indirect access. a write to the indirect link address register triggers an indirect access and sets lbusy to logic 1. lbusy stays high until the access is completed. at which point, lbusy will be set low. this register should be polled to determine either: (1) when data from an indirect read operation is available in the indirect data register or (2) when a new indirect write operation may commence.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 171 register 0x072: rttc indirect link configuration register bit type function default 15:11 unused 10 r/w lcdoocdpass 0 9 r/w hcspass 0 8 r/w unasspass 0 7 r/w idlepass 0 6 r/w ddscr 0 5 r/w reserved 0 4 r/w reserved 0 3 r/w oocde 0 2 r/w hcse 0 1r/w fovre 0 0 r/w lcde 0 this register contains either: (1) data read from the rttc link provision ram after an indirect link read operation or (2) data to be inserted into the rttc link provision ram in an indirect link write operation. the bits to be written to the rttc link provision ram, in an indirect link write operation, must be set up in this register before triggering the write. the bits reflect the value written until the completion of a subsequent indirect link read operation. the reset state of the bits enables standard atm cell processing as stipulated in itu-t recommendation i.432.1 lcde: the lcde bit enables the generation of an interrupt due to a change in the lcd state. when lcde is set to logic 1, the interrupt is enabled. fovre: the fovre bit enables the generation of an interrupt due to a fifo overrun error condition. when fovre is set to logic 1, the interrupt is enabled.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 172 hcse: the hcse bit enables the generation of an interrupt due to the detection of an hcs error. when hcse is set to logic 1, the interrupt is enabled. oocde: the oocde bit enables the generation of an interrupt due to a change in the cell delineation state. when oocde is set to logic 1, the interrupt is enabled. ddscr: the ddscr bit controls the descrambling of the cell payload with the polynomial x 43 + 1. when ddscr is set to logic 1, cell payload descrambling is disabled. when ddscr is set to logic 0, payload descrambling is enabled. idlepass: the idlepass bit controls the function of the idle cell filter. when idlepass is written with a logic 0, all idle cells (i.e., the first four bytes of a cell: x00, x00, x00, and x01) are filtered out. when idlepass is logic 1, idle cells are passed to the external cell buffer. unasspass: when unasspass is written with a logic 0, all unassigned cells (i.e., the first four bytes of a cell: x00, x00, x00, and x00) are filtered out. when unasspass is logic 1, unassigned cells are passed to on the external cell buffer. hcspass: the hcspass bit controls the dropping of cells based on the detection of an hcs error. when hcspass is logic 0, cells containing an hcs error are dropped. when hcspass is a logic 1, cells are passed to the external cell buffer regardless of errors detected in the hcs. lcdoocdpass: the lcdocdpass bit controls the dropping of cells based on the detection of an out of cell delineation and loss of cell delineation. when lcdoocdpass is logic 0, cells containing an oocd error and an lcd error are dropped. when lcdoocdpass is a logic 1, cells are passed to the external cell buffer regardless of errors detected in the oocd and lcd.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 173 register 0x074: rttc indirect link interrupt and status register bit type function default 15:6 unused 5 r oocdv 1 4 r lcdv 0 3 r oocdi 0 2 r hcsi 0 1r fovri 0 0 r lcdi 0 this register contains data read from the rttc link provision ram after an indirect read operation. lcdi: the lcdi bit is set high when there is a change in the loss of cell delineation (lcd) state. this bit is reset immediately after a read to this register. fovri: the fovri bit is set to logic 1 when a fifo overrun occurs. this bit is reset immediately after a read to this register. hcsi: the hcsi bit is set high when an hcs error is detected. this bit is reset immediately after a read to this register. oocdi: the oocdi bit is set high when the logical link enters or exits the sync state. the oocdv bit indicates whether the logical link is in the sync state or not. the oocdi bit is reset immediately after a read to this register. lcdv: the lcdv bit gives the loss of cell delineation state. when lcd is logic 1, an out of cell delineation (ocd) defect has persisted for the number of cells specified in the lcd count threshold register. when lcd is logic 0, no ocd has persisted for the number of cells specified in the lcd count threshold
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 174 register. the cell time period can be varied by using the lcdc[7:0] register bits in the lcd count threshold register. oocdv: the oocdv bit is high when the logical link is not currently in the sync state.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 175 register 0x076: rttc indirect link hcs error count register bit type function default 15:0 r hcserr[15:0] 0 this register contains data read from the rttc link provision ram after an indirect read operation. hcserr[15:0]: the hcserr[7:0] bits indicate the number of hcs error events that occurred during the last accumulation interval. when the number of hcs error events during the last accumulation interval exceeds 64k, the hcserr[15:0] retains a value of ffffh until the next accumulation interval (hcserr[15:0] is reset).
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 176 register 0x078: lcd count threshold bit type function default 15:8 unused 7:0 r/w lcdc[7:0] 0x68 lcdc[7:0]: the lcdc[7:0] bits represent the number of consecutive cell periods the receive cell processor must be out of cell delineation before loss of cell delineation (lcd) is declared. likewise, lcd is not deasserted until the receive cell processor is in cell delineation for the number of cell periods specified by lcdc[7:0]. the default value of lcdc[7:0] is 104; this translates to 28 ms at 1.5 mbps.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 177 11.6 sbi registers register 0x080: sbi bus configuration register (sbi_bus_cfg_reg) bit type function default 15:14 rsvd unused 0 13 r/w reserved 0 12 r/w reserved 0 11 r/w reserved 0 10 r/w reserved 0 9 r/w reserved 0 8 r/w spe3_enbl 0 7 r/w spe2_enbl 0 6 r/w spe1_enbl 0 5:4 r/w spe3_typ[1:0] 0 3:2 r/w spe2_typ[1:0] 0 1:0 r/w spe1_typ[1:0] 0 the sbi bus contains 3 synchronous payload envelopes (spe) that can be configured to be e1, t1, or ds3. this register defines the payload type for each spe, and enables each spe. spen_typ[1:0] the spen_typ fields identify the payload type of each spe. the encoding for spen_type is: payload type spen_typ value t1 b?00? e1 b?01? ds3 b?10? reserved b?11?
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 178 spen_enbl the spen_enbl field is used to enable or disable an entire spe on the sbi. when high, the spe is enabled. all spes default to disabled.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 179 register 0x084-0x08e: sbi extract alarm interrupt register address bit type function default 0x084 15:0 r2c spe1_alrm_int[15:0] 0 15:12 r2c unused 0 0x086 11:0 r2c spe1_alrm_int[27:16] 0 0x088 15:0 r2c spe2_alrm_int[15:0] 0 15:12 r2c unused 0 0x08a 11:0 r2c spe2_alrm_int[27:16] 0 0x08c 15:0 r2c spe3_alrm_int[15:0] 0 15:12 r2c unused 0 0x08e 11:0 r2c spe3_alrm_int[27:16] 0 spen_alrm_intn when set, spen_alrm_intn indicates that the alm bit in the v4 octet received on the sbi drop bus has changed on the corresponding sbi tributary. this bit is cleared upon reading. read spen_alrm_statn to see the current state. when a bit is set in any spen_alrm_intn and the sbi_alarm_en bit is set, the sbi_alarm bit will be set in the master interrupt register; this will activate intb.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 180 register 0x090-0x09a: sbi extract alarm status register address bit type function default 0x090 15:0 ro spe1_alrm_stat[15:0] 0 15:12 ro unused 0 0x092 11:0 ro spe1_alrm_stat[27:16] 0 0x094 15:0 ro spe2_alrm_stat[15:0] 0 15:12 ro unused 0 0x096 11:0 ro spe2_alrm_stat[27:16] 0 0x098 15:0 ro spe3_alrm_stat[15:0] 0 15:12 ro unused 0 0x09a 11:0 ro spe3_alrm_stat[27:16] 0 spen_alrm_statn spen_alrm_statn indicates the current value of the alm bit received in the v4 octet of the sbi drop bus on the corresponding sbi tributary. spe1_alrm_intn in the sbi extract alarm interrupt register will be set whenever this bit changes.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 181 register 0x0a0: sbi extract control register bit type function default 15:8 unused 0 7 r/w reserved 0 6 r/w dc_enbl 1 5 r/w dc_int_en 0 4 r/w fifo_ovre 0 3 r/w fifo_udre 0 2 r/w reserved 0 1 r/w sbi_perr_en 0 0 r/w sbi_par_ctl 1 sbi_par_ctl the sbi_par_ctl bit is used to configure the parity mode for checking the sbi parity signal dp as follows: when sbi_par_ctl is ?0?, parity will be even. when sbi_par_ctl is ?1?, parity will be odd. sbi_perr_en the sbi_perr_en bit is used to enable sbi parity error interrupt generation. when sbi_perr_en is ?0?, sbi parity error interrupts will be disabled. when sbi_perr_en is ?1?, sbi parity error interrupts will be enabled. in both cases, the sbi parity checker logic will update the sbi parity error interrupt reason register. fifo_udre this bit is set to enable the generation of an interrupt when a fifo underrun is detected. fifo_ovre this bit is set to enable the generation of an interrupt when a fifo overrun is detected.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 182 dc_int_en this bit is set to enable the generation of an interrupt when either of the following events occurs: a depth check error an external resynchronization event occurs on either the c1fp or sbiip_sync signals dc_enbl this bit enables automatic depth check resets. the depth-checker logic will periodically monitor the exsbi fifo depths and compare them to the write and read pointers. when dc_enbl is asserted high and there is a discrepancy, the tributary is automatically reset by the depth checker. when dc_enbl is low, the tributary reset is suppressed, but the depth check error is reported via the depth check interrupt reason register.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 183 register 0x0a2: sbi extract fifo underrun interrupt register bit type function default 15:8 unused 0 7:6 r2c spe[1:0] 01 5:1 r2c trib[4:0] 0 0 r2c fifo_udri 0 fifo_udri this bit is set when a fifo underrun is detected, regardless of the state of exsbi fifo_udre. reading this register clears this bit unless another fifo underrun interrupt is pending. trib[4:0] and spe[1:0] the trib[4:0] and spe[1:0] fields specify the sbi tributary on which the fifo underrun was detected. legal values for trib[4:0] are b?00001? through b?11100?. legal values for spe[1:0] are b?01? through b?11?. these fields are valid only when fifo_udri=1.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 184 register 0x0a4: sbi extract fifo overrun interrupt register bit type function default 15:8 unused 0 7:6 r2c spe[1:0] 01 5:1 r2c trib[4:0] 0 0 r2c fifo_ovri 0 fifo_ovri this bit is set when a fifo overrun is detected, regardless of the state of exsbi fifo_ovre. reading this register clears this bit unless another fifo overrun interrupt is pending. trib[4:0] and spe[1:0] the trib[4:0] and spe[1:0] fields specify the sbi tributary on which the fifo overrun was detected. legal values for trib[4:0] are b?00001? through b?11100?. legal values for spe[1:0] are b?01? through b?11?. these fields are valid only when fifo_ovri=1.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 185 register 0x0a6: sbi extract tributary control ram indirect access address register bit type function default 15:8 unused 0 7 r/w reserved 0 6:5 r/w spe[1:0] 0 4:0 r/w trib[4:0] 0 trib[4:0] and spe[1:0] the trib[4:0] and spe[1:0] fields are used to specify to which sbi tributary the control register access will apply. trib[4:0] specifies the sbi tributary number within the sbi spe as specified by the spe[1:0] field. legal values for trib[4:0] are b?00001? through b?11100?. legal values for spe[1:0] are b?01? through b?11?.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 186 register 0x0a8: sbi extract tributary control ram indirect access control register bit type function default 15:8 unused 0 7ro busy 0 6 r2c hst_addr_err 0 5:2 unused 0 1r/wrwb 0 0 r/w reserved 0 rwb the indirect access control bit (rwb) selects between a configure (write) or an interrogate (read) access to the tributary control configuration ram. writing a ?0? to rwb triggers an indirect write operation. data to be written is taken from the sbi extract tributary control indirect access data register. writing a ?1? to rwb triggers an indirect read operation. the data read can be found in the sbi extract tributary control indirect access data register. hst_addr_err when set following a host read, this bit indicates that an illegal host access was attempted. an illegal host access occurs when an attempt is made to access an out-of-range tributary. for ds3 the out-of-range tributaries are 1,2 to 1,28; 2,2 to 2,28; and 3,2 to 3,28. for e1, the out-of-range tributaries are 1,22 to 1,28; 2,22 to 2,28; and 3,22 to 3,28. busy the indirect access status bit (busy) reports the progress of an indirect access. busy is set high when a write to the sbi extract tributary ram indirect access control register triggers an indirect access and will stay high until the access is complete. this register should be polled to determine either: (1) when data from an indirect read operation is available in the indirect tributary data register or (2) when a new indirect write operation may commence. .
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 187 register 0x0ac: sbi extract tributary control ram indirect access data register bit type function default 15:7 unused 0 6 r/w reserved 0 5 r/w reserved 0 4 r/w reserved 0 3:2 r/w trib_typ[1:0] 0 1 r/w reserved 0 0 r/w enbl 0 this register represents either (1) the data to be written to the internal memory or (2) data read from the internal memory from the previous indirect read operation. the read data is not valid until the busy bit in the sbi extract tributary ram indirect access control register is cleared. enbl the enbl bit is used to enable the tributary. writing to an sbi extract tributary control register with the enbl bit set enables the exsbi to take tributary data from an sbi tributary and transmit that data to the corresponding link fifo. trib_typ[1:0] the trib_typ[1:0] field is used to specify the characteristics of the sbi tributary. only the value of ?01? is supported; this indicates a framed tributary without cas. this must be written to a ?01? value. note: any write to a tributary control register for a tributary will generate a configuration reset on that tributary, irrespective of whether the data written to the tributary control register is unchanged from the previous value.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 188 register 0x0ae: sbi extract parity error interrupt register bit type function default 15:8 unused 0 7:6 ro spe[1:0] 01 5:1 ro trib[4:0] 00001 0 r2c perri 0 perri this bit is set when an sbi parity error is detected, regardless of the state of sbi_perr_en. reading this register clears this bit unless another parity error interrupt is pending. trib[4:0] and spe[1:0] the trib[4:0] and spe[1:0] fields specify the sbi tributary on which the parity error was detected. legal values for trib[4:0] are b?00001? through b?11100?. legal values for spe[1:0] are b?01? through b?11?. these fields are valid only when perri=1
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 189 register 0x0bc: sbi extract depth check interrupt register bit type function default 15:8 unused 0 7:6 r2c spe[1:0] 01 5:1 r2c trib[4:0] 0 0 r2c dcr_inti 0 dcr_inti this bit is set when a depth check error is detected, regardless of the state of dc_int_en. reading this register clears this bit unless another depth check interrupt is pending. trib[4:0] and spe[1:0] the trib[4:0] and spe[1:0] fields specify the sbi tributary on which the depth check error was detected. legal values for trib[4:0] are b?00001? through b?11100?. legal values for spe[1:0] are b?01? through b?11?. these fields are valid only when dcr_inti=1.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 190 register 0x0be: sbi extract master interrupt register bit type function default 15:8 unused 0 7 rw fifo_underun_dis 0 6 rsvd unused 0 5 ro dcr_inti_shdw 0 4 ro perri_shdw 0 3 ro fifo_udri_shdw 0 2 ro fifo_ovri_shdw 0 1 r2c sbiip_sync_inti 0 0 r2c c1fp_sync_inti 0 c1fp_sync_inti this bit is set when a c1fp realignment has been detected. reading this register clears this interrupt source. sbiip_sync_inti this bit is set when a sbiip_sync realignment has been detected. reading this register clears this interrupt source. fifo_ovri_shdw this bit is a shadow of the fifo_ovri bit in the sbi extract fifo overrun interrupt status register. it is set when the fifo_ovri bit is set and the interrupt enable fifo_ovre is set. reading this register has no affect on this interrupt source. fifo_udri_shdw this bit is a shadow of the fifo_udri bit in the sbi extract fifo underrun interrupt status register. it is set when the fifo_udri bit is set and the interrupt enable fifo_udre is set. reading this register has no affect on this interrupt source.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 191 perri_shdw this bit is a shadow of the perri bit in the sbi parity error interrupt reason register. it is set when the perri bit is set and the interrupt enable sbi_perr_en is set. reading this register has no affect on this interrupt source. dcr_inti_shdw this bit is a shadow of the dcr_inti bit in the sbi extract depth check interrupt status register. it is set when the dcr_inti bit is set and the interrupt enable dcr_int_en is set. reading this register has no affect on this interrupt source. fifo_underun_dis this bit, when set, disables underrun errors by not playing data out of an internal rate matching fifo when the fifo goes empty. if this bit is not set, depth check interrupts will occur and data corruption will result. note: this bit must be set to a one for proper operation
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 192 register 0x0c0: sbi insert control register bit type function default 15:8 unused 0 7 r/w reserved 0 6 r/w dc_enbl 1 5 r/w dc_int_en 0 4 r/w fifo_ovre 0 3 r/w fifo_udre 0 2 r/w reserved 0 1 rsvd unused 0 0 r/w sbi_par_ctl 1 sbi_par_ctl the sbi_par_ctl bit is used to configure the parity mode for generation of the sbi data parity signal, adp as follows when sbi_par_ctl is a ?0? parity will be even. when sbi_par_ctl is a ?1?, parity will be odd. fifo_udre the fifo_udre bit is used to enable/disable the generation of an interrupt when a fifo underrun is detected. when fifo_udre is a ?0?, underrun interrupt generation is disabled. when fifo_udre is a ?1?, underrun interrupt generation is enabled. fifo_ovre the fifo_ovre bit is used to enable/disable the generation of an interrupt when a fifo overrun is detected. when fifo_ovre is a ?0?, overrun interrupt generation is disabled. when fifo_ovre is a ?1?, overrun interrupt generation is enabled. dc_int_en this bit is set to enable the generation of an interrupt when either of the following events occurs: a depth check error
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 193 an external resynchronization event occurs on either the c1fp or sbiip_sync signals dc_enbl this bit enables automatic depth check resets. the depth-checker logic will periodically monitor the exsbi fifo depths and compare them to the write and read pointers. when dc_enbl is asserted high and there is a discrepancy, the tributary is automatically reset by the depth checker. when dc_enbl is low, the tributary reset is suppressed, but the depth check error is reported via the depth check interrupt reason register.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 194 register 0x0c2: sbi insert fifo underrun interrupt register bit type function default 15:8 unused 0 7:6 ro spe[1:0] 01 5:1 ro trib[4:0] 0 0 r2c fifo_udri 0 fifo_udri this bit is set when a fifo underrun is detected, regardless of the state of insbi fifo_udre. reading this register clears this bit unless another fifo underrun interrupt is pending. trib[4:0] and spe[1:0] the trib[4:0] and spe[1:0] fields specify the sbi tributary on which the fifo underrun was detected. legal values for trib[4:0] are b?00001? through b?11100?. legal values for spe[1:0] are b?01? through b?11?. these fields are valid only when fifo_udri=1.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 195 register 0x0c4: sbi insert fifo overrun interrupt register bit type function default 15:8 unused 0 7:6 ro spe[1:0] 01 5:1 ro trib[4:0] 0 0 r2c fifo_ovri 0 fifo_ovri this bit is set when a fifo overrun is detected, regardless of the state of insbi fifo_ovre. reading this register clears this bit unless another fifo overrun interrupt is pending. trib[4:0] and spe[1:0] the trib[4:0] and spe[1:0] fields specify the sbi tributary on which the fifo overrun was detected. legal values for trib[4:0] are b?00001? through b?11100?. legal values for spe[1:0] are b?01? through b?11?. these fields are valid only when fifo_ovri=1.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 196 register 0x0c6: sbi insert tributary control ram indirect access address register bit type function default 15:8 unused 0 7 r/w reserved 0 6:5 r/w spe[1:0] 0 4:0 r/w trib[4:0] 0 trib[4:0] and spe[1:0] the trib[4:0] and spe[1:0] fields are used to fully specify the sbi tributary to which the control ram write or read operation will apply. trib[4:0] specifies the sbi tributary number within the sbi spe, as specified by the spe[1:0] field. legal values for trib[4:0] are b?00001? through b?11100?. legal values for spe[1:0] are b?01? through b?11?.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 197 register 0x0c8: sbi insert tributary control ram indirect access control register bit type function default 15:8 unused 0 7ro busy 0 6 r2c hst_addr_err 0 5:2 unused 0 1r/wrwb 0 0 r/w reserved 0 rwb the indirect access control bit (rwb) selects between a configure (write) or interrogate (read) access to the control configuration ram. writing a ?0? to rwb triggers an indirect write operation. data to be written is taken from the sbi insert tributary control indirect access data register. writing a ?1? to rwb triggers an indirect read operation. the data read can be found in the sbi insert tributary control indirect access data register. hst_addr_err when set following a host read, this bit indicates that an illegal host access was attempted. an illegal host access occurs when an attempt is made to access an out-of-range tributary. busy the indirect access status bit (busy) reports the progress of an indirect access. busy is set high when a write to the sbi insert tributary ram indirect access control register triggers an indirect access and will stay high until the access is complete. this register should be polled to determine either: (1) when data from an indirect read operation is available in the indirect tributary data register or (2) to determine when a new indirect write operation may commence.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 198 register 0x0cc: sbi insert tributary control ram indirect access data register bit type function default 15:6 unused 0 5 r/w reserved 0 4 r/w reserved 0 3:2 r/w trib_typ[1:0] 0 1 r/w reserved 0 0 r/w enbl 0 this register represents either (1) the data to be written to the internal memory or (2) data read from the internal memory from the previous indirect read operation. the read data is not valid until the busy bit in the sbi insert tributary ram indirect access control register is cleared. enbl the enbl bit is used to enable the tributary. writing to an sbi insert tributary control ram location with the enbl bit set enables the insbi to take tributary data from a link fifo and transmit that data to the corresponding sbi tributary. trib_typ[1:0] the trib_typ[1:0] field is used to specify the characteristics of the sbi tributary. only the value ?01? (which indicates a framed tributary) is valid. ? cas can only be enabled for a framed tributary. ? a transparent vt can not be a framed tributary ? a transparent vt can not have cas. ? ?framed? means framing information available ? may be channelized or unchannelized. ? ?unframed? means no framing information available.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 199 ? ?floating transparent vts? uses all possible sbi octets for data except v1-v4. ? for ds3 and e3 there is no cas and no transparent vt modes. only framed and unframed modes are used. the msb of trib_typ is used to determine if the tributary is framed or unframed. the lsb of trib_typ is ignored. ? for fractional tributaries the trib_typ field is ignored. note: any write to a tributary control ram location for a tributary will generate a configuration reset on that tributary, irrespective of whether the data written to the tributary control ram location is unchanged from the previous value.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 200 register 0x0e2: sbi insert depth check interrupt register bit type function default 15:8 unused 0 7:6 ro spe[1:0] 01 5:1 ro trib[4:0] 0 0 r2c dcr_inti 0 dcr_inti this bit is set when a depth check error is detected, regardless of the state of dc_int_en. reading this register clears this bit unless another depth check interrupt is pending. trib[4:0] and spe[1:0] the trib[4:0] and spe[1:0] fields specify the sbi tributary on which the depth check error was detected. legal values for trib[4:0] are b?00001? through b?11100?. legal values for spe[1:0] are b?01? through b?11?. these fields are valid only when dcr_inti=1.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 201 register 0x0e4: sbi insert master interrupt register bit type function default 15:6 unused 0 5 ro dcr_inti_shdw 0 4 rsvd unused 0 3 ro fifo_udri_shdw 0 2 ro fifo_ovri_shdw 0 1 r2c sbiip_sync_inti 0 0 r2c c1fp_sync_inti 0 c1fp_sync_inti this bit is set when a c1fp realignment has been detected. sbiip_sync_inti this bit is set when a sbiip_sync realignment has been detected. this generally happens when the sbi interface is configured and indicates an internal bus sync event. after configuration, this interrupt should not occur. fifo_ovri_shdw this bit is a shadow of the fifo_ovri bit in the sbi insert fifo over run interrupt status register. it is set when the fifo_ovri bit is set and the interrupt enable fifo_ovre is set. reading this register has no affect on the interrupt status. fifo_udri_shdw this bit is a shadow of the fifo_udri bit in the sbi insert fifo under run interrupt status register. it is set when the fifo_udri bit is set and the interrupt enable fifo_udre is set. reading this register has no affect on the interrupt status. dcr_inti_shdw this bit is a shadow of the dcr_inti bit in the sbi insert depth check interrupt status register. it is set when the dcr_inti bit is set and the interrupt enable dcr_int_en is set. reading this register has no affect on the interrupt status.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 202 this register will contain the interrupt status, even if the corresponding interrupt enable is not set.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 203 11.7 line clock/data interface register 0x100: rcas indirect link and time-slot control register bit type function default 15 r busy x 14 r/w rwb 0 13 r/w unused 0 12:8 r/w link[4:0] 0 7:5 unused x 4:0 r/w tslot[4:0] 00 this register provides the link number and time-slot number used to access the time-slot provision ram. writing to this register triggers an indirect register access. tslot[4:0]: the indirect time-slot number bits (tslot[4:0]) indicate the time-slot to be configured or interrogated in the indirect access. for a channelized t1 link, time-slots 1 to 24 are valid. for a channelized e1 link, time-slots 1 to 31 are valid. for unchannelized links, only time-slot 0 is valid. link[4:0]: the indirect link number bits (link[4:0]) select amongst the 32 receive links to be configured or interrogated in the indirect access. rwb: the indirect access control bit (rwb) selects between a configure (write) or interrogate (read) access to the timeslot provision ram. the address to the timeslot provision ram is constructed by concatenating the tslot[4:0] and link[4:0] bits. writing a logic zero to rwb triggers an indirect write operation. data to be written is taken from the prov, the vldlben, and the vlink[6:0] bits of the indirect link data register. writing a logic one to rwb triggers an indirect read operation. addressing of the ram is the same as in an indirect write operation. the data read can be found in the prov, the vldlben, and the vlink[6:0] bits of the indirect link data register.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 204 busy: the indirect access status bit (busy) reports the progress of an indirect access. busy is set high when this register is written; this is done to trigger an indirect access, and will stay high until the access is complete. at which point, busy will be set low. this register should be polled to determine either: (1) when data from an indirect read operation is available in the indirect data register or (2) when a new indirect write operation may commence.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 205 register 0x102: rcas indirect link data register bit type function default 15:10 r unused x 9 r/w vldlben 0 8r/w prov 0 7 unused x 6:0 r/w vlink[6:0] 00 the rcas timeslot provision ram maps either timeslots from a physical link or an entire physical link to a virtual link. it also provisions timeslots/links and enables diagnostic loopback. this register contains either: (1) the data read from the rcas timeslot provision ram after an indirect read operation or (2) the data to be inserted into the rcas timeslot provision ram during an indirect write operation. vlink[6:0] vlink[6:0] is the virtual link to which this rcas link/tslot is mapped. valid values are 0x00 to 0x53. for proper operation, timeslots from multiple physical links cannot be mapped to the same vlink. after an indirect read operation has been completed, vlink[6:0]) reports the virtual link number read from the rcas timeslot provision ram. the virtual link number to be written to the rcas timeslot provision ram in an indirect write operation must be set up in this register before triggering the write. vlink[6:0] reflects the value written until the completion of a subsequent indirect read operation. prov the indirect provision enable bit (prov) reports the timeslot provision enable flag read from the timeslot provision ram after an indirect read operation has been completed. the provision enable flag to be written to the timeslot provision ram in an indirect write operation must be set up in this register before triggering the write. when prov is set high, the current receive data byte is processed as part of the virtual link (as indicated by vlink[6:0]). when prov is set low, the current time-slot does not belong to any virtual
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 206 link and the receive data byte is ignored. prov reflects the value written until the completion of a subsequent indirect read operation. vldlben when the indirect virtual link based diagnostic loopback enable bit vldlben=1, the current receive data byte will be over-written by a data byte retrieved from the loopback fifo of the virtual link as indicated by vlink[6:0]. when vldlben=0, the current receive data byte is processed normally. vldlben reports the value read from the rcas timeslot provision ram after an indirect read operation has been completed. vldlben must be set up in this register before triggering an indirect write. vldlben reflects the value written until the completion of a subsequent indirect read operation.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 207 register 0x104: rcas framing bit threshold bit type function default 15:7 r unused x 6:0 r/w fthres[6:0] 0x3f this register contains the threshold used by the clock-activity monitor to detect framing bits/bytes. fthres[6:0] the framing bit threshold bits (fthres[6:0]) contain the threshold used by the clock activity monitor to detect for the presence of framing bits. a counter in the clock-activity monitor increments at each refclk and is cleared by a rising edge of the rsclk. when the counter exceeds the threshold given by fthres[6:0], a framing bit/byte has been detected. fthres[6:0] should be set as a function of the refclk period and the expected gapping width of rsclk during framing bits/bytes. for e1 only device operation, the following equation should be used to determine the acceptable range of values for fthres: 7 * . 1 . . 5 . 1 * . 1 . . < < freq e rsclk freq refclk fthres freq e rsclk freq refclk for t1 device operation and mixed t1 and e1 device operation (t1 requirements are more rigorous), the following equation should be used to determine fthres: 5 . 1 * . 1 . . freq t rsclk freq refclk fthres
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 208 register 0x106: rcas link disable bit type function default 15 r vldis 0 14:7 unused x 6:0 r/w dvlink[6:0] 0 this register allows the squelching of output data from a particular virtual link. dvlink[6:0]: the disable virtual link bits (dvlink[6:0]) specify the virtual link whose output data from the rcas are to be squelched. when vldis is set high, the virtual link specified by dvlink[6:0] is disabled, even if the virtual link is provisioned. vldis: when set high, the virtual link disable bit (vldis) squelches valid data on the output of rcas for the virtual link indicated by dvlink[6:0].
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 209 register 0x140- 0x17e: rcas link #0 to link #31 configuration bit type function default 15:3 r unused x 2 r/w reserved 0 1r/w e1 0 0r/w cen 0 this register configures operational modes of receive link #0 to link #31 (rsdata[n]/ rsclk[n] where 0 n 31). cen: the channelize enable bit (cen) configures link #n for channelized operation. when cen=1, rsclk[n] must be gapped during the t1 framing bit and during the e1 framing byte. the data bit on rsdata[n] that is clocked in by the first rising edge of rsclk[n] after an extended low period is considered to be the most significant bit of time-slot 1. when cen=0, link #n is unchannelized. the e1 register bit is ignored. rsclk[n] must be gapped during non-data bits. all data bits are treated as a contiguous stream with arbitrary byte alignment. e1: the e1 frame structure select bit (e1) configures link #n for channelized e1 operation when cen is set high. rsclk[n] is held low during the fas and nfas framing bytes. the data bit on rsdata[n] that is associated with the first rising edge of rsclk[n] after an extended low period is considered to be the most significant bit of time-slot 1. link data is present at time-slots 1 to 31. when e1 is set low and cen is set high, link #n is configured for channelized t1 operation. rsclk[n] is held low during the framing bit. the data bit on rsdata[n] that is associated with the first rising edge of rsclk[n] after an extended low period is considered to be the most significant bit of time-slot 1. link data is present at time-slots 1 to 24. e1 is ignored when cen is set low.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 210 register 0x180: tcas indirect link and time-slot control register bit type function default 15 ro busy x 14 r/w rwb 0 13 unused x 12:8 r/w link[4:0] 0 7:5 unused x 4:0 r/w tslot[4:0] 0 this register provides the link number and time-slot number used to access the timeslot provision ram. writing to this register triggers an indirect register access and transfers the contents of the indirect link data register to an internal holding register. tslot[4:0] the indirect time-slot number bits (tslot[4:0]) indicate the time-slot to be configured or interrogated in the indirect access. for a channelized t1 link, time-slots 1 to 24 are valid. for a channelized e1 link, time-slots 1 to 31 are valid. for unchannelized links, only time-slot 0 is valid. link[4:0] the indirect link number bits (link[4:0]) select amongst the 32 transmit links to be either configured or interrogated in the indirect access. rwb the indirect access control bit (rwb) selects between a configure (write) or interrogate (read) access to the timeslot provision ram. the address to the timeslot provision ram is constructed by concatenating the tslot[4:0] and link[4:0] bits. writing a logic zero to rwb triggers an indirect write operation. data to be written is taken from the prov and the vlink[6:0] bits of the indirect data register. writing a logic one to rwb triggers an indirect read operation. addressing of the ram is the same as in an indirect write operation. the data read can be found in the prov and the vlink[60] bits of the indirect link data register after the busy bit has cleared.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 211 busy the indirect access status bit (busy) reports the progress of an indirect access. busy is set high when this register is written to trigger an indirect access, and will stay high until the access is complete. at which point, busy will be cleared (low). alternatively, busy will be set high when tcas first comes out of reset until the ram has been initialized. this register should be polled to determine either: (1) when data from an indirect read operation is available in the indirect data register or (2) when a new indirect write operation may commence. any indirect operation that is initiated while busy is still high will be corrupted.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 212 register 0x182: tcas indirect link data register bit type function default 15:9 unused x 8r/w prov 0 7 unused x 6:0 r/w vlink[6:0] 0 the tcas timeslot provision ram maps virtual links to either timeslots in a physical link or to an entire physical link. it also provisions timeslots. this register contains either: (1) the data read from the tcas timeslot provision ram after an indirect read operation or (2) the data to be inserted into the tcas timeslot provision ram during an indirect write operation. vlink[6:0] vlink[6:0] is the virtual link from which this tcas link/tslot is mapped. valid values are 0x00 to 0x53. for proper operation, timeslots from multiple physical links cannot be mapped to the same vlink. after an indirect read operation has been completed, vlink[6:0]) reports the virtual link number read from the tcas timeslot provision ram. the virtual link number to be written to the tcas timeslot provision ram in an indirect write operation must be set up in this register before triggering the write. vlink[6:0] reflects the value written until the completion of a subsequent indirect read operation. prov the indirect provision enable bit (prov) reports the timeslot provision enable flag read from the timeslot provision ram after an indirect read operation has been completed. the provision enable flag to be written to the timeslot provision ram in an indirect write operation must be set up in this register before triggering the write. when prov is set high, the current time-slot is assigned to the virtual link as indicated by vlink[6:0]. when prov is set low, the time-slot does not belong to any virtual link. the transmit link data is set to the contents of the idle time-slot fill data register. prov reflects the last value read or written until the completion of a subsequent indirect read operation.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 213 register 0x184: tcas framing bit threshold bit type function default 15:7 unused x 6:0 r/w fthres[6:0] 0x1f this register contains the threshold used by the clock activity monitor to detect for framing bits/bytes. fthres[6:0] the framing bit threshold bits (fthres[6:0]) contains the threshold used by the clock activity monitor to detect the presence of framing bits. a counter in the clock activity monitor increments at each refclk and is cleared by a rising edge of the tsclk. when the counter exceeds the threshold given by fthres[6:0], a framing bit/byte has been detected. fthres[6:0] should be set as a function of the refclk period and the expected gapping width of tsclk during framing bits/bytes. for e1 only device operation, the following equation should be used to determine the acceptable range of values for fthres: 7 * . 1 . . 5 . 1 * . 1 . . < < freq e tsclk freq refclk fthres freq e tsclk freq refclk for t1 device operation and mixed t1 and e1 device operation (t1 requirements are more rigorous), the following equation should be used to determine fthres: 5 . 1 * . 1 . . freq t tsclk freq refclk fthres
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 214 register 0x186: tcas idle time-slot fill data bit type function default 15:8 unused x 7:0 r/w fdata[7:0] 0xff this register contains the data to be written to the disabled time-slots of a channelized link. fdata[7:0] the fill data bits (fdata[7:0]) are transmitted during disabled (prov set low) time-slots or virtual links.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 215 register 0x188: tcas link disable register bit type function default 15 r/w vldis 0 14:7 unused x 6:0 r/w dvlink[6:0] 0 this register indicates a virtual link that is to be disabled (unprovisioned) while individual time-slots are changed. this allows virtual links to either turn on or off at once instead of gradually while each time-slot in the provisioning ram is written. dvlink[6:0] the disable virtual link bits (dvlink[6:0]) indicate the virtual link to be disabled. if vldis=1, all time-slots mapped to this virtual link will be forced unprovisioned, and the value in fdata[7:0] will be transmitted. vldis the virtual link disable bit (vldis) disables the virtual link in dvlink[6:0]. when vldis=1, all time-slots mapped to dvlink[6:0] will be forced unprovisioned, and the prov bit of those time-slots will be ignored. when vldis=0, the virtual link's provisioning state is set by the prov bit.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 216 register 0x1c0 ? 0x1fe: tcas link #0 to link #31 configuration bit type function default 15:3 unused x 2 r/w reserved 0 1r/w e1 0 0r/w cen 0 this register configures the operational modes of transmit link #0 to link # 31 (tsdata[n] / tsclk[n]; where 0 n 31 = ). cen the channelize enable bit (cen) configures link #n for channelized operation. when cen=1, tsclk[n] must be gapped during the t1 framing bit or the e1 framing byte. thus, on the first rising edge of tsclk[n] after the extended low period, a downstream device can sample the msb of timeslot one. when cen=0, link #n is unchannelized, and the e1 register bit is ignored. tsclk[n] can be gapped during non-data bits, and all data bits are treated as a contiguous stream without regard to timeslots. e1 the e1 frame structure select bit (e1) configures link #n for channelized e1 operation when cen is set high. tsclk[n] is held low during the fas and nfas framing bytes. the most significant bit of time-slot 1 is placed on tsdata[n] on the last falling edge of tsclk[n] ahead of the extended low period. link data is present at time-slots 1 to 31. when e1 is set low and cen is set high, link #n is configured for channelized t1 operation. tsclk[n] is held low during the framing bit. the msb of time-slot 1 is placed on tsdata[n] on the last falling edge of tsclk[n] ahead of the extended low period. link data is present at time-slots 1 to 24. e1 is ignored when cen is set low.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 217 11.8 ripp registers register 0x200:ripp control bit type function default 15 r/w ripp_en 0 14 r/w reserved 0 13 r ripp_busy 0 12:0 reserved 0 ripp_busy this is a status signal indicating that the ripp main-state machine is currently active. this bit is generated by ripp. ripp_en the ripp_en enables the ripp main state machine for normal operations. when ripp_en = 0 and ripp_busy = 0, all ripp operations are disabled. the ripp_en should be set to a ?1? for normal operations after the initialization of ripp context memory.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 218 register 0x202:ripp indirect memory access control bit type function default 15 ro mem_busy 0 14 r/w mem_rwb 0 13 r/w mem_sel 0 12:10 reserved 9:0 r/w mem_addr 0 this register controls the indirect access to the internal memory. there are two separate rams used by ripp. one is the configuration memory, which holds the configuration information for all groups and links programmed by the microprocessor; the other is the context memory, which stores the state context used as the working space for the ripp internal state machine. each of them is 32-bits wide and contains 1024 words. mem_addr: the indirect memory address (mem_addr [9:0]) indicates the memory word address to be read or written. the memory-address organization of the internal rams is shown in table 5 and table 6. table 5 configuration memory address space address space description 0x000 ? 0x29f group configuration record area. 0x2a0 ? 0x2f3 tx link configuration record area. 0x2f4 ? 0x34f reserved 0x350 ? 0x3a3 rx link configuration record area. 0x3a5 ? 0x3ff reserved
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 219 table 6 context memory address space address space description 0x000 ? 0x29f group context record area. 0x2a0 ? 0x347 tx link context record area. 0x348 ? 0x34f reserved 0x350 ? 0x3f7 rx link context record area. 0x3f8 ? 0x3ff reserved mem_sel: the memory select (mem_sel) is used to select between the two internal rams. a logic ?0? selects the configuration memory, while a logic ?1? selects the context memory. mem_rwb: the memory indirect access control bit (mem_rwb) selects between a configure (write) or interrogate (read) access to the ripp internal context ram. writing a logic 0 to mem_rwb triggers an indirect write operation. data to be written is taken from the ripp indirect memory data registers. writing a logic 1 to mem_rwb triggers an indirect read operation. the read data can be found in the ripp indirect channel data registers mem_busy: the memory indirect access status bit (mem_busy) reports the progress of an indirect access. to trigger an indirect access, mem_busy is set high when this register is written; it stays high until the access is complete; at that point, mem_busy is set low. this register should be polled to determine either: (1) when data from an indirect read operation is available in the indirect data register or (2) when a new indirect write operation may commence.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 220 register 0x204 ? 0x206:ripp indirect memory data register array address bit type function default 0x204 15:0 r/w mem_data_lsb 0 0x206 15:0 r/w mem_data_msb 0 mem_data_lsb: the mem_data_lsb represents either: (1) the least significant 16 bits of the data to be written to internal memory or (2) the least significant 16 bits of the read data resulting from the previous read operation. the read data is not valid until after the mem_busy bit has been cleared. mem_data_msb: the mem_data_msb represents either: (1) the most significant 16 bits of the data to be written to internal memory or (2) the least significant 16 bits of the read data resulting from the previous read operation. the read data is not valid until after the mem_busy bit has been cleared. the actual memory data structure is shown in table 7 through table 13.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 221 ripp group configuration record memory purpose: contains the pm programmed configuration data for the corresponding groups. usage: ima groups only. maintained by: pm. record size: 16 32-bit words. mem_addr = area_base_address + group_tag * 0x10 + word offset table 7 ripp group configuration record structure word bit data field description 0 31:24 ima_oam_label ima oam label value for the group. this indicates the ima version for the current group, and is used to compare against the ima version number carried in octet 6 of the incoming icp cells.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 222 word bit data field description 23:22 group_sym_mo de group symmetry mode. this is programmed by pm during group configuration. it is then used by ripp to compare against the group symmetry mode field in the incoming icp cells during group start-up process. if the two values do not match, the start-up process will be aborted. this field is also inserted into outgoing icp cells. the supported values for this field are: ?00?: symmetrical configuration and operation ?01?: symmetrical configuration and asymmetrical operation ?10?: asymmetrical configuration and asymmetrical operation ?11?: reserved 21 group_icp_fwd _en group icp cell forwarding enable. ?0?: disable icp cell forwarding to pm. ?1?: enable icp cell forwarding to pm. an interrupt will be generated upon each icp cell to be forwarded to pm, and the content of the icp cell will be copied to microprocessor?s directly accessible registers. 20 group_icp_fwd_fi lter group icp cell forwarding filtering enable. ?0?: no filtering. all icp cells from rdat will be forwarded to pm. ?1?: filtering. ripp will filter out the icp cells which carry no new information (determined by the scci field) before forwarding to pm.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 223 word bit data field description 19 ima_10_enable ima version 1.0 style link state reporting enable. this field selects how the link state field in the incoming and outgoing icp cells should be interpreted. note that this bit will be ignored if the group is in asymmetric configuration mode. ?0?: ima version 1.1 style (default) ?1? ima version 1.0 style. 18:10 reserved 9 pm_adjust_dela y_done_int_en pm adjust delay procedure done interrupt enable ?0? interrupt not enabled ?1? interrupt enabled. 8 fe_trl_int_en invalid rx trl interrupt enable ?0? interrupt not enabled ?1? interrupt enabled. 7 group_timing_i nt_en group timing interrupt enable ?0? interrupt not enabled ?1? interrupt enabled. 6 fe_timeout_int_ en fe timeout interrupt enable: ?0? interrupt not enabled ?1? interrupt enabled. 5 group_timeout _int_en group timeout enable. ?0? interrupt not enabled ?1? interrupt enabled. 4 fe_abort_int_e n fe abort interrupt enable. ?0? interrupt not enabled ?1? interrupt enabled.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 224 word bit data field description 3 ne_abort_int_e n ne abort interrupt enable ?0? interrupt not enabled ?1? interrupt enabled. 2 gtsm_int_en gtsm interrupt enable ?0? interrupt not enabled ?1? interrupt enabled. 1 fe_gsm_int_en fe gsm interrupt enable ?0? interrupt not enabled ?1? interrupt enabled. 0 ne_gsm_int_en ne gsm interrupt enable ?0? interrupt not enabled ?1? interrupt enabled. 1 31:24 tx_ima_id ima id value to use in the tx (outgoing) icp cells. this field is programmed by pm during group record initialization. 23:22 tx_m transmit ima frame length (m). used by tima in the transmit ima operation. ?00?: m = 32 ?01?: m = 64 ?10?: m = 128 ?11?: m = 256 21:16 p_tx minimum number of active tx links required in the group in order for the group to be operational. 15:8 tx_end_channe l tx end-to-end channel. this data field is used by ripp to generate the end- to-end channel field in the outgoing icp cells.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 225 word bit data field description 7 tx_clk_mode transmit clock mode. ?0?: itc mode. ?1?: ctc mode. this field is used in the outgoing tx icp cells. note the actual clock mode used by tima may differ from this. after a group is added, this field should not be changed, unless a group restart is to be issued. 6:0 reserved 2 31:25 reserved 24 rx_ima_id_cfg_e n this bit selects whether the ima id value used in the rx direction should be configured by pm or captured from incoming icp cells. ?0?: ima id captured from icp cells and saved in context memory (rx_ima_id_cap). ?1?: ima id configured by pm in the rx_ima_id_cfg field in the configuration memory. 23:16 rx_ima_id_cfg rx ima id value programmed by pm. 15:14 reserved 13:8 p_rx minimum number of active rx links required in the group in order for the group to be operational. 7:4 reserved
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 226 word bit data field description 3:0 rx_m_range 4-bit vector indicating the m values deemed acceptable. used during group parameter negotiation. bit 3: m = 256 (?0?: unacceptable, ?1?: acceptable) bit 2: m = 128 (?0?: unacceptable, ?1?: acceptable) bit 1: m = 64 (?0?: unacceptable, ?1?: acceptable) bit 0: m = 32 (?0?: unacceptable, ?1?: acceptable) 3 31:26 reserved 25:16 rx_delay_tol receive differential delay tolerance. this field is the maximum allowed amount of delay to be accumulated for a link within the group. this threshold will be used in determining if links are acceptable for adding to a group. this value must be set at least 8 cells greater than the rx_delay_guardband. 15:11 reserved 10 rx_add_delay_e n receive ima group delay-adding enable. when enabled, the ripp will roll back the rdat read pointers, which effectively adds more delay to the group, in order to accommodate the new link if it is necessary. ?0?: disabled. ?1?: enabled.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 227 word bit data field description 9:0 rx_delay_guar d_band receive ima group link differential delay guard-band value. this is the suggested distance between rdat cell write pointer on the slowest link and the rdat cell read pointer (expressed in the unit of cells), which is set by ripp when it activates the rx data path during group start-up. this value is not used after group start-up. a guardband placed at group startup will help allow admittance of slower links later. note that this is only a recommended behavior; if necessary, ripp may choose to not to maintain this guard band in order to accept a slow link. 4 31:0 reserved
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 228 word bit data field description 5:15 31:0 rx_phy_table this table contains the physical link numbers of all rx links assigned to the group by pm. the table has 32 entries that are packed into 11 32-bit words; each entry corresponds to one rx link. the order of links in the table is determined by pm prior to group start-up, and is not related to the lids or physical link numbers. entries in this table correspond to bits in the rx_link_vec. see table 8 for the detailed bit mapping. in symmetrical configuration mode, this table needs to be configured identical to the tima transmit-lid-to- physical-link mapping table , where the physical link pointers are loaded into the table indexed by the tx lid (i.e. if tx lid 2 was assigned tx physical link 45, then rx physical link pointer 2 would be set to 45). in asymmetrical configuration mode, this table may be loaded in any order, regardless of the tx physical link pointers or rx lid values, as long as the entries correspond to bits in the rx_link_vec. a simple method for loading entries into this table is to begin at zero and fill the table from there (although holes will appear as links are deleted).
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 229 table 8 rx physical link table word bit description 0 31:27 reserved 26:20 rx physical link pointer 2 19:17 reserved 16:10 rx physical link pointer 1 9:7 reserved 6:0 rx physical link pointer 0 ?? ?.. word 11 31:17 reserved 16:10 rx physical link pointer 31 9:7 reserved 6:0 rx physical link pointer 30
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 230 ripp tx link configuration record memory purpose: contains the pm programmed configuration data for the corresponding tx links. usage: ima groups only. maintained by: pm. record size: 1 32-bit word. mem_addr = area_base_address + physical link number * 0x1+ word offset table 9 ripp tx link configuration record structure word bit data field description 0 31:23 reserved 22:16 tx_link_group_ tag group tag value of the group which this tx physical link has been assigned to. this field is programmed by pm during link record initialization. 15:11 tx_lid lid value for the physical link. this field is programmed by pm during link record initialization. 10:5 reserved 4 tx_active_int_e n tx active interrupt enable. ?0? interrupt not enabled ?1? interrupt enabled. 3 fe_rx_unusable _int_en fe rx unusable interrupt enable. ?0? interrupt not enabled ?1? interrupt enabled. 2 fe_rx_defect_i nt_en fe rx defect interrupt enable. ?0? interrupt not enabled ?1? interrupt enabled.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 231 word bit data field description 1 tx_timeout_int_ en tx_timeout interrupt enable. ?0? interrupt not enabled ?1? interrupt enabled. reserved
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 232 ripp rx link configuration record memory purpose: contains the pm programmed configuration data for the corresponding rx links. usage: ima groups only. maintained by: pm. record size: 1 32-bit word. mem_addr = area_base_address + physical link number * 0x1+ word offset table 10 ripp rx link configuration record structure word bit data field description 0 31:23 reserved 22:16 rx_link_group_ tag group tag value of the group to which this rx physical link has been assigned. this field is programmed by pm during link record initialization. 15:11 reserved 10 rx_active_int_e n rx active interrupt enable. ?0? interrupt not enabled ?1? interrupt enabled. 9 idle_cell_int_e n idle cell interrupt enable. ?0? interrupt not enabled ?1? interrupt enabled. 8 fe_tx_unusable _int_en fe tx unusable interrupt enable ?0? interrupt not enabled ?1? interrupt enabled. 7 diff_delay_int_ en differential delay interrupt enable ?0? interrupt not enabled ?1? interrupt enabled.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 233 word bit data field description 6 lods_overrun_i nt_en lods, dcb overrun interrupt enable ?0? interrupt not enabled ?1? interrupt enabled. 5 lods_underrun _int_en lods, dcb under- interrupt enable ?0? interrupt not enabled ?1? interrupt enabled. 4 lcd_int_en lcd interrupt enable ?0? interrupt not enabled ?1? interrupt enabled. 3 lif_int_en lif interrupt enable ?0? interrupt not enabled ?1? interrupt enabled. 2 invalid_icp_int_ en invalid_icp interrupt enable ?0? interrupt not enabled ?1? interrupt enabled. 1 rx_timeout_int rx timeout interrupt enable. ?0? interrupt not enabled ?1? interrupt enabled. 0 reserved
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 234 ripp group context record memory purpose: contains the current state machine states and status information for the corresponding groups. usage: ima groups only. maintained by: ripp. record size: 16 32-bit words. mem_addr = area_base_address + group_tag * 0x10 + word offset unless otherwise specified, all data and the reserved fields should be cleared (to all ?0?s) by pm prior to adding the group; they will be cleared by ripp during a group restart process table 11 ripp group context record structure word bit data field description 031 group_en indicates if the current group is enabled. this bit is set by pm using the add_group command, and cleared by pm using the delete_group command. ?0?: not enabled (group in not_configured state) ?1?: the group is enabled and currently active. this field will remain at its current value during a group-restart.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 235 word bit data field description 30:27 gsm group state machine state. ?0000?: start-up ?0001?: start-up-ack ?0010?: config-aborted ? unsupported m ?0011?: config-aborted ? incompatible group symmetry ?0100?: config-aborted ? unsupported ima versions ?0111?: config-aborted ? other reasons ?1000?: insufficient-links ?1001?: blocked ?1010?: operational others: reserved 26:24 reserved 23 gtsm group traffic state machine state ?0?: down (no atm data transmission is allowed) ?1?: up (atm data transmission is allowed) 22:21 gwp_active group wide procedure in progress. ?00?: no group-wide procedure is currently in progress. ?01?: group start-up procedure is in progress. ?10?: lasr is in progress. others: reserved 20 reserved
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 236 word bit data field description 19 lsm_sync_tran s indicates whether there has been a transition on the lsm_sync state machine in the last processing cycle for the group. ?0?: there was no transition. ?1?: there was a transition. 18:16 lsm_sync current state of lsm_sync state machine, which is used to synchronize lsm transition during group startup and lasr procedure. "000": idle "001": lsm_sync_getm (group parameter negotiation finished). "010": lsm_sync_rx_usable (rx ready to go to usable state, delay evaluation needed). "011": lsm_sync_rx_active_rdat (rx ready to start receiving, starting rdat and idcc) "100": lsm_sync_rx_active (rx ready to report active to fe) "101": lsm_sync_tx_active (tx ready to report active to fe) 15:12 fe_gsm far-end gsm states. this is copied from the group state field in the incoming icp cells 11:6 num_tx_links_a ctive total number of tx links that are currently in an active state. 5:0 num_rx_links_ active total number of rx links that are currently in an active state.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 237 word bit data field description 131 group_timer_e n1 group timer 1 enable. the enable bit is set when the timer is loaded; it is cleared when either a timeout occurs or the timer is disabled. 30:28 reserved 27:24 group_timer1 group-level timer 1. implemented as 4- bit down counter. the counter is loaded with the appropriate timeout value when the timer is enabled, and decrements on every timer tick, until it reaches zero. a timeout event is declared when a timer tick occurs and the counter equals zero, if the timer is enabled. 23 group_timer_e n2 group timer 2 enable. the enable bit is set when timer is loaded; it is cleared when either a timeout occurs or the timer is disabled. 22:20 reserved 19:16 group_timer2 group-level timer 2. implemented as 4- bit down counter. the counter is loaded with the appropriate timeout value when the timer is enabled, and decrements on every timer tick, until it reaches zero. a timeout event is declared when a timer tick occurs and the counter equals to zero, if the timer is enabled.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 238 word bit data field description 15 group_int_acti ve indicates whether there is currently an interrupt active from the group (including all the links). this bit is set to ?1? by ripp upon generating a interrupt and cleared upon pm issuing a read_event command. no new interrupt will be generated once this bit is set. this field will remain at its current value during a group-restart. 14 group_inhibit_ status group inhibiting status. ?0?: group is not inhibited. ?1?: group is inhibited. this field can be programmed by pm during group record initialization, and can be modified later using inhibit_group/not_inhibit_group commands. note it is possible to inhibit the group before actually issuing the add_group command. this field will remain at its current value during a group-restart. 13 reserved
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 239 word bit data field description 12 fe_trl_status when set, indicates that the trl specified in the last received icp cell is a link that is ?in_group?. if the trl received in the last icp cell is not ?in_group?, this bit is cleared, and the trl remains with the last specified valid trl. during the period in which the specified trl is not ?in_group?, the scheduling of the cells played out to the atm layer is not accurate and the depth of the dcb buffers may drift and cause dcb buffer overruns or underruns. if on group startup, the trl is not detected to be ?in_group?, the group will not start up. 11 group_timing_ error group timing error. the fe ima transmit clock mode does not match the ne transmit clock mode. 10 reserved 9 pm_adjust_del y_int pm adjust_delay procedure done interrupt. the adjust_delay procedure invoked by the pm command has successfully finished or aborted. 8 fe_trl_int fe trl interrupt. thefe_trl_status bit has changed state. 7 grp_timing_int group timing interrupt. the group_timing_error has changed state. 6 fe_timeout_int startup-ack timeout: the fe fails to transition into the startup-ack state prior to the ne timing out. 5 gr_timeout_int gsm fails to come out of insufficient- links state during a group start-up procedure before the relevant timer expires.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 240 word bit data field description 4 fe_abort_int fe entered config-aborted state during group start-up. 3 ne_abort_int entered ne config aborted state. fe group parameters unacceptable during group start-up. possible causes are ima oam label proposed by fe not acceptable. group symmetry proposed by fe not acceptable. rx m proposed by fe not acceptable 2 gtsm_int gtsm state change. 1 fe_gsm_int fe gsm state change. 0 ne_gsm_int ne gsm state change. 2 31:24 tx_scci current tx scci value for the group. each time the tx icp cell class b&c info changes, the scci field increments by one. this field will remain at its current value during a group-restart. 23:16 tx_rx_test_pt n tx test pattern field to be sent in the transmit icp cell. if the test link command active bit in the incoming icp cell from rdat is set, this field is updated using the tx test pattern field in the same icp cell; otherwise this field is set to ?ff? internally. this field will remain at its current value during a group-restart. 15:7 reserved
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 241 word bit data field description 6:0 tx_trl_phy_id physical link id for tx trl. this field need to be programmed by pm prior to group startup to ensure tx idcc ticks are generated and tima start sending icp cells once the group is added. once a group is added, the trl can be changed by using update_tx_trl command. this field will remain at its current value during a group-restart. 3 31:25 reserved 24 tx_gsm_2frame indicates whether at least 2 tx frames has been transmitted since the last time we have a gsm change. this is used to make sure the group status and info field stays the same for at least 2 tx frames, as stated in ima spec. ?0?: less than 2 frames have been transmitted since the last gsm transition. ?1?: at least 2 frames have been transmitted since the last gsm transition. 23:16 tx_last_gsm_t rans_ifsn the tx frame sequence number being transmitted last time there is a gsm transition.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 242 word bit data field description 15 tx_test_en enable tx test pattern procedure. ?0?: disabled. the test pattern field in the outgoing icp cells will be filled with zeros. ?1?: enabled. ripp will copy the stored tx_test_pattern info over to the test pattern field. this field is set and changed using the update_test_ptn pm command. this field will remain at its current value during a group-restart. 14:13 reserved 12:8 tx_test_lid tx lid of the test link. this field is set and changed using the update_test_ptn pm command. this field will remain at its current value during a group-restart. 7:0 tx_tx_test_ptn tx test pattern field to be sent in the transmit icp cell. this field is set and changed using the update_test_ptn pm command. this field will remain at its current value during a group-restart.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 243 word bit data field description 4 31:0 tx_phy_valid 32 bit vector in which each bit corresponds to one tx physical link in the tima transmit lid to physical link mapping table ?0?: table entry not valid ?1?: table entry valid (physical link pointed by the corresponding tx_phy_table entry has been assigned to the current group.) this field will remain at its current value during a group-restart. 5 31:0 tx_lasr_act 32 bit vector in which each bit corresponds to one tx physical link in the tima transmit lid to physical link mapping table. ?0?: the link is not currently involved in a lasr procedure. ?1?: the link is currently involved in an active lasr procedure. 6 31:30 reserved 29 rx_fe_info_vali d this indicates whether the context data fields captured from incoming icp cells) or not. ?0?: invalid. ?1?: valid. this bit is set internally by ripp during group start-up upon capturing the first valid incoming icp cells. this field will remain at its current value during a group-restart. 28 reserved
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 244 word bit data field description 27:26 rx_m receive ima frame length (m). this parameter is captured from incoming icp cells during group-start-up negotiation process, and later used by rdat in the receive ima operation. ?00?: m = 32 ?01?: m = 64 ?10?: m = 128 ?11?: m = 256 25:24 fe_sym_mode group symmetrical mode as indicated by the fe in the latest icp cell analyzed 23:16 fe_ima_oam_la bel ima oam label value as indicated by the fe in the latest icp cell analyzed 15:8 rx_scci current rx scci value for the group. this value is captured from the incoming icp cells and used to determine whether the icp cell should be processed. this field will remain at its current value during a group-restart. 7:0 rx_ima_id stores the rx_ima_id. the value may be copied from the rx_ima_id_cfg field in the configuration memory if the rx_ima_id_cfg_en bit is set, otherwise it is captured from the first incoming icp cell after the group is added or restarted.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 245 word bit data field description 7 31:0 rx_phy_valid 32 bit vector in which each bit corresponds to one rx physical link in rx_phy_table. ?0?: table entry not valid ?1?: table entry valid (physical link pointed by the corresponding rx_phy_table entry has been assigned to the current group). this field is cleared by pm during group record initialization. it may be modified during normal operations by issuing the appropriate pm command, such as add_group, add_link, delete_group, delete_link. this field will remain at its current value during a group-restart. 8 31:0 rx_lasr_act 32 bit vector in which each bit corresponds to one rx physical link in rx_phy_table (which is located in ripp group configuration memory). ?0?: the link is not involved in lasr. ?1?: the link is currently involved in a active lasr procedure.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 246 word bit data field description 9 31:0 rx_test_ptn_m atch 32 bit vector in which each bit corresponds to the current test pattern match result on one rx link. the order of rx links is defined in rx_phy_table (which is located in the ripp group configuration memory). ?0?: the rx_test_pattern field in the incoming icp cells on the link does not match the tx_test_pattern field in the outgoing icp cells. ?1?: the rx_test_pattern field in the incoming icp cells on the link matches the tx_test_pattern field in the outgoing icp cells. 10 31:0 rx_lid_alloc 32 bit vector in which each bit indicates whether the lid value represented by the bit index is occupied. for example, bit 31 corresponds to lid value 31, bit 0 corresponds to lid 0, and so on. ?0?: lid has not been allocated to any links. ?1?: lid has been allocated to one of the rx links in the group. 11 31 rx_tx_test_cm d the tx_test_cmd field captured from incoming icp cells. 30:29 reserved 28:24 rx_tx_test_lid the tx_test_lid field captured from incoming icp cells. 23:7 reserved
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 247 word bit data field description 6:0 last_scci_phy_link _id physical link id of the rx link on which the last ?analyzable? icp cell comes. a icp cell is considered analyzable if 1). the current processing cycle is icp and 2). the icp cell is valid, and 3). the icp cell carries a new scci, or the icp cell comes from the same link of the last analyzed icp cell; and 4). rx_ima_id matches the configured value (or if no value is configured, the value captured from the first icp cell if group is started/restarted) 12 31 rx_trl_valid this indicates whether in the rx idcc the trl of the current group has been turned on or not. trl is identified by the rx_trl_phy_id field, which is translated from the tx_trl_ lid in the incoming icp cells, after it is validated by ripp. ?0?: invalid. trl off. ?1?: valid. trl on. this bit is set internally by ripp when it first turns on the trl in rx idcc (when lsm_sync reaches the right state and trl lid has been validated). it is possible for the fe to change the trl_lid during normal operations, in which case the new trl lid will be verified again and saved. 30:23 reserved
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 248 word bit data field description 22:16 rx_trl_phy_id receive timing reference physical link id. rx_trl_phy_id is translated via a lookup into the rx_phy_table using the trl_lid field in the incoming icp cells, and then used to control the rx idcc. 15:13 reserved 12:8 rx_trl_lid the trl lid info captured from incoming icp cells. 7 delay_adjust_ active indicates whether a adjust_delay procedure is current active. adjust delay could be started by pm command adjust_delay, or internally by lasr procedure. ?0?: no delay adjustment is in progress. ?1?: delay adjustment is in progress. 6 delay_adjust_ rdat_toggle the last value of the delay_toggle bit read from rdat group context memory. a transition on this bit is used to determine the ongoing adjust_delay process is finished. 5 delay_adjust_i s_pm indicates whether the current adjust_delay process is started by pm. ?0?: the adjust-delay is started internally by lasr. ?1? the adjust-delay is started by pm. 4:0 reserved 10:15 31:0 reserved
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 249 ripp tx link context record memory purpose: contains the current state machine states and status information for the corresponding tx links. usage: ima groups only. maintained by: ripp. record size: 2 32-bit words. mem_addr = area_base_address + physical link number * 0x2 + word offset unless otherwise specified, all the data fields and the reserved fields should be cleared (to all ?0?s) by pm prior to adding the link, and will be internally cleared by ripp during a group-restart. table 12 ripp tx link context record structure word bit data field description 031 tx_link_en flag bit indicating whether the link is enabled or not. ?0?: not enabled, link in unassigned state ?1: enabled. this field is set by ripp during add_link or add_group command processing. it is cleared by ripp upon finishing deleting the link. it may be polled by pm to determine the progress of link addition or deletion. this field will remain at its current value during a group-restart.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 250 word bit data field description 30:27 tx_lsm tx link state machine state. ?0000?: deleted(not_in_group) ?0010?: unusable ?1100?: usable ?1110?: active others: reserved this field is cleared by pm during link record initialization. 26:16 reserved 15 tx_link_timer_e n tx link timer enable. the enable bit is set when the timer is loaded; it is cleared when either a timeout occurs or the timer is disabled. 14:12 reserved 11:8 tx_link_timer tx link timer. implemented as 4-bit down counter. the counter is loaded with the appropriate timeout value when the timer is enabled, and decrements on every timer tick, until it reaches zero. a timeout event is declared when a timer tick occurs and the counter equals zero, if the timer is enabled. 7 reserved 6:4 fe_rx_lsm far end rx lsm state for the link. this is copied from the appropriate tx lsm state field in the incoming icp cells.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 251 word bit data field description 3 tx_link_pm_unu sable this field indicates the link has been considered unusable by pm. this bit is set up on pm issuing unusable_link command, and cleared up on pm issuing recover_link command. this field is programmed by pm during link record initialization. this field will remain at its current value during a group-restart. 2:0 tx_link_pm_unu sable_cause cause specified by pm for the link to be unusable. this field is used by ripp to notify fe. ?000?: no cause specified ?010?: fault. ?011?: mis-connected ?100?: inhibited ?101?: failed others: reserved (currently considered the same as no cause specified). this field is programmed by pm during link record initialization. this field will remain at its current value during a group-restart. 1 31:10 reserved
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 252 word bit data field description 9:8 fe_rx_defect defect status reported in last receive icp cell. 00) no defect 01) physical link defect (e.g. los, oof/lof, lcd) 10) lif 11) lods 7:5 reserved 4 tx_active_int indicates that the ne tx lsm transitioned into/out of active state. this bit is reset immediately after the read_event command is executed for the group of which this link is a member. 3 fe_rx_unusable _int indicates that fe rx lsm transitioned into/out of unusable state. this bit is reset immediately after read_event command is executed for the group of which this link is a member. 2 fe_rx_defect_i nt indicates that the fe rx defect indication changed. this bit is reset immediately after read_event command is executed for the group of which this link is a member. 1 tx_timeout_int indicates the lasr procedure timed out prior to the link entering the active state. this bit is reset immediately after read_event command is executed for the group of which this link is a member. 0 reserved
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 253 ripp rx link context record memory purpose: contains the current state machine states and status information for the corresponding rx links. usage: ima groups only. maintained by: ripp. record size: 2 32-bit words. mem_addr = area_base_address + physical link number * 0x2 + word offset unless otherwise specified, all the data fields and the reserved fields should be cleared (to all ?0?s) by pm prior to adding the link, and internally cleared by ripp during group restart. table 13 ripp rx link context record structure word bit data field description 031 rx_link_en flag bit indicating if the link is enabled or not. ?0?: not enabled, link in unassigned state. ?1: enabled. this field is set by ripp during add_link or add_group command processing. it is cleared by ripp upon finishing deleting the link. it may be polled by pm to determine the progress of link addition or deletion. this field will remain at its current value during a group-restart.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 254 word bit data field description 30:25 rx_lsm rx link state machine state. ?000000?: start_up, no m has been negotiated yet. ?000010?: deleted, waiting for fe ?000100?: deleted, waiting for dcb underrun ?000110?: unusable_no_lid (report to fe as not_in_group) ?001000?: unusable ?001010?: unusable, waiting for dcb underrun ?001100?: blocking, waiting for fe ?110000?: usable ?110010?: usable, waiting for data in dcb to be played out, reporting usable. ?110011?: usable, waiting for fe ?110100?: active, waiting for rx cell reader to become active, reporting usable. ?110110?: active, waiting for the global synchronization event to report active to the fe. ?111000: active, reporting active others: reserved this field is cleared (unassigned state) by pm during link record initialization. the link_pm_unusable_cause will be used to encode the unusable states in outgoing icp cells. the value transmitted in the icp cell is a combination of part of the rx_lsm d part of the link_pm_unusable_cause.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 255 word bit data field description 24 reserved 23 rx_lid_valid flag bit indicating if the value in the rx_lid field is valid or not. ?0?: invalid ?1: valid. this field is cleared by pm during link record initialization. it will be set by ripp upon the success of rdat lid validation. 22:21 reserved 20:16 rx_lid lid value for the rx physical link. this field is cleared by pm during link record initialization. it will be set by ripp upon the success of rdat lid validation. 15 rx_link_timer_ en rx link timer enable. the enable bit is set when the timer is loaded; it is cleared when either a timeout occurs or the timer is disabled. 14:12 reserved 11:8 rx_link_timer rx link timer. implemented as 4-bit down counter. the counter is loaded with the appropriate timeout value when the timer is enabled, and decrements on every timer tick, until it reaches zero. a timeout event is declared when a timer tick occurs and the counter equals zero, if the timer is enabled. 7 reserved 6:4 fe_tx_lsm far end tx lsm state for the link. this is copied from the appropriate tx lsm state field in the incoming icp cells.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 256 word bit data field description 3 rx_link_pm_un usable this field indicates the link has been considered unusable by pm. this bit is set up on pm issuing unusable_link command, and cleared upon pm issuing recover_link command. this field is programmed by pm during link record initialization. this field will remain at its current value during a group-restart. 2:0 rx_link_pm_un usable_cause cause specified by pm for the link to be unusable. this field is used by ripp to notify fe. ?000?: no cause specified ?010?: fault. ?011?: mis-connected ?100?: inhibited ?101?: failed others: reserved (currently considered the same as no cause specified). this field is programmed by pm during link record initialization. this field will remain at its current value during a group-restart. 1 31:21 reserved 20 link_delay_go od the result of the last differential delay evaluation for the link.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 257 word bit data field description 19 lods_ovr lods, dcb overrun. indicates that the dcb buffer is in an overrun condition. this occurs when the transport delay for the link is detected to be outside the programmed limit and the transport delay is longer than the other links within the group. 18 lods_underru n lods, dcb under-run. indicates that the dcb buffer is in an underrun condition. 17 lcd lcd, loss of cell delineation defect is present on this link. 16 lif lif, a loss of ima frame defect condition is present on this link. 15:11 reserved 10 rx_active_int rx lsm transition into/out of active state. this bit is reset immediately after read_event command is executed for the group of which this link is a member. 9 idle_cell_int physical layer idle cells were received on the rx link. this bit is reset immediately after read_event command is executed for the group of which this link is a member. 8 fe_tx_unusabl e_int fe tx lsm transitioned into or out of the unusable state. this bit is reset immediately after the read_event command is executed for the group of which this link is a member.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 258 word bit data field description 7 diff_delay_int differential delay is out of bounds on link addition/or recovery. this indicates the delay on the link was out of bounds of the programmed differential delay and the link failed to come up for this reason. this bit is reset immediately after the read_event command is executed for the group of which this link is a member. 6 lods_overrun_ int lods, dcb overrun. an overrun condition occurred. this bit is reset immediately after read_event command is executed for the group of which this link is a member. 5 lods_underru n_int lods, dcb underrun. indicates that the dcb buffer experienced an underrun condition and has disabled itself from forwarding traffic to the atm layer. an underrun occurs when the transport delay for the link is detected to be outside the programmed limit and the transport delay is smaller than the other links within the group in general, this will happen only if the transport delay of the link changes. an underrun condition requires that the link delay be revalidated prior to being placed back in service. this bit is reset immediately after the read_event command is executed for the group of which this link is a member.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 259 word bit data field description 4 lcd_int a change of state of the lcd status bit was detected. this bit is reset immediately after read_event command is executed for the group of which this link is a member. 3 lif_int a change of state of the lif status bit was detected. this bit is reset immediately after read_event command is executed for the group of which this link is a member. 2 invalid_icp _int invalid icp parameters detected on rx link during validation of the icp cell parameters causing validation to fail. possible reasons include: invalid lid (i.e., duplicate). invalid icp cell offset (out of range). invalid rx ima id, which may indicate a misconnectivity problem. invalid oam label received after ima version being determined through negotiation. invalid group symmetry received after symmetry being determined through negotiation. this bit is reset immediately after read_event command is executed for the group of which this link is a member.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 260 word bit data field description 1 rx_timeout_int indicates the lasr procedure timed out prior to the link entering the active state. this bit is reset immediately after the read_event command is executed for the group of which this link is a member. 0 invalid_fe_tx_i nt invalid fe tx lsm states were detected in a incoming non-errored icp cell. this bit is reset immediately after the read_event command is executed for the group of which this link is a member.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 261 register 0x20c: ripp timer tick configuration register bit type function default 15:0 r/w timer_tick_interval 0x3473 timer-tick_interval this value controls the interval between timer tick events. the timer ticks are internally generated by counting sysclk pulses. the count of sysclk pulses between sysclk pulses is a 26 bit integer, the most significant 16 bits of which are specified here, and the lower 10-bits are set to ?0?s internally. to give an example, a timer_tick_interval value of 0 x 3473 represents a value of 0xd1cc00 (13,749,248 decimal) sysclk pulses; this translates to about 275 milliseconds in real time assuming a 50 mhz sysclk.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 262 register 0x20e: group timeout register #1 bit type function default 15:12 r/w group_startup_ack_timeout 0x4 11:8 r/w group_config_abort_timeout 0x4 7:4 r/w rx_usable_timeout 0x4 3:0 r/w rx_active_timeout 0x4 this register holds the time-out values used at different states of the group state machine or the group-wide procedures (such as group start-up and lasr). the actual time represented by the timeout value in this register can be obtained as: real_time = timeout_value * internal_timer_tick_interval group_config_abort_timeout: the timeout value determines how long the gsm should stay in config_aborted state before it can move back to start-up state, if no new parameters are proposed by the fe and pm does not issue a restart_group command. group_startup_ack_timeout: the timeout value determines how long the gsm should stay in start-up-ack state before it can move back to start-up state, if the fe gsm is not in one of the following states: start-up-ack, insufficient-links, blocked, or operational. rx_usable_timeout: during the group start-up or lasr, this timeout value determines how long the ripp should wait before it can move any rx lsms to usable state (unless all the rx links involved are out of defect status). in the case of group start-up, the timer is started when the gsm enters insufficient-links state; during lasr, it is started when the pm issues add_link command. rx_active_timeout: during the group start-up or lasr, this timeout value determines how long the ripp should wait before it can move any rx lsms to active state (unless all the links involved are being reported tx = usable by the fe). the timer is started after the rx = usable synchronization point.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 263 register 0x210: group timeout register #2 bit type function default 15:4 reserved 3:0 r/w tx_active_timeout 0x4 this register holds additional group time-out values. tx_active_timeout: during the group start-up or lasr, this value determines how long the ripp should wait before it can move any tx lsms to active state (unless all the links involved are being reported rx = usable by the fe). in the case of group start-up, the timer is started when the gsm enters insufficient-links state; during lasr, it is started when the pm issues add_link command.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 264 register 0x212: tx link timeout register bit type function default 15:4 r/w reserved 0 3:0 r/w tx_link_deleted_timeout 0x4 this register holds the time-out values used at different states of the tx lsm. the actual time represented by the timeout value in this register can be obtained as: real_time = timeout_value * internal_timer_tick_interval tx_link_deleted_timeout: during link deletion, this value determines how long the tx lsm should stay in the deleted state before it can move to the unassigned state (if the fe does not report rx != active).
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 265 register 0x214: rx link timeout register bit type function default 15:8 r/w reserved 0 7:4 r/w rx_link_blocked_timeout 0x4 3:0 r/w rx_link_deleted_timeout 0x4 this register holds additional time-out values used at different states of the rx lsm. the actual time represented by the timeout value in this register can be obtained as: real_time = timeout_value * internal_timer_tick_interval rx_link_deleted_timeout: in the case of link deletion, this value determines how long the rx lsm should stay in the deleted state before it can move to the unassigned state (if the fe does not report tx != active). rx_link_blocked_timeout: in the case of link inhibiting, this value determines how long the rx lsm should stay in the blocked state before it can move to the unusable state (if the fe does not report tx != active).
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 266 register 0x216: ripp interrupt fifo bit type function default 15 ro fifo_busy 0 14 ro fifo_not_empty 0 13:8 reserved 7:0 ro group tag 0 this register is the read interface to the ripp interrupt fifo. each read to this register causes a read to the fifo, which automatically updates this register. group_tag: group_tag identifies the group that generated the interrupt. group_tag is valid only if fifo_not_empty=1 and fifo_busy=0. fifo_not_empty current fifo status. fifo_not_empty=1 means the fifo is not empty; and fifo_not_empty=0 means the fifo is empty. fifo_not_empty is valid only if fifo_busy=0. fifo_busy indicates that the fifo is busy retrieving the next entry. fifo_busy will usually clear within four sysclk cycles from the end of a read.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 267 register 0x218:ripp group interrupt enable register bit type function default 15:10 r/w reserved 0 9 r/w pm_adjust_delay_do ne_int_en 0 8 r/w invalid_trl_int_en 0 7r/w grp_timing_int_en0 6 r/w fe_timeout_int_en 0 5 r/w gr_timeout_int_en 0 4 r/w fe_abort_int_en 0 3 r/w ne_abort_int_en 0 2r/w gtsm_int_en 0 1 r/w fe_gsm_int_en 0 0 r/w ne_gsm_int_en 0 the above enable bits provides a global enable for the corresponding ima group interrupts. if an interrupt enable bit is not set, the respective interrupt is disabled for all groups. if a bit is set, the individual group interrupt enable is used. 0 ? disable group interrupt for all links. 1? use individual group interrupt enable.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 268 register 0x21a:ripp tx link interrupt enable register bit type function default 15:5 r/w reserved 1 4 r/w tx_active_int_en 3 r/w fe_rx_unusable_int_ en 2 r/w fe_rx_defect_int_en 1 r/w tx_timeout_int_en 0 r/w unused the above enable bits provides a global enable for the corresponding tx link interrupts. if an interrupt enable bit is not set, the respective interrupt is disabled for all links. if a bit is set, the individual tx link interrupt enable is used. 0 ? disable corresponding tx link interrupt for all links. 1 ? use individual corresponding tx link interrupt enable.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 269 register 0x21c:ripp rx link interrupt enable register bit type function default 15:11 r/w reserved 0 10 r/w rx_active_int_en 0 9 r/w idle_cell_int_en 0 8 r/w fe_tx_unusable_int_ en 0 7 r/w diff_delay_int_en 0 6 r/w lods_overrun_int_e n 0 5 r/w lods_underrun_int_ en 0 4 r/w lcd_int_en 0 3r/w lif_int_en 0 2 r/w invalid_icp_int_en 0 1 r/w rx_timeout_int_en 0 0 r/w unused 0 the above enable bits provide a global enable for the corresponding rx link interrupts. if an interrupt enable bit is not set, the respective interrupt is disabled for all links. if a bit is set, the individual rx link interrupt enable is used. 0 ? disable group link interrupt for all links. 1 ? use individual link interrupt enable for each link.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 270 register 0x220-22c: ripp command register address bit type function default 0x220 15 ro cmd_busy 0 14:10 r/w cmd_code 0 9rocmd_ack 0 8 reserved 7:0 r/w cmd_wr_data00 0 0x222 15:0 r/w cmd_wr_data01_lsb 0 0x224 15:0 r/w cmd_wr_data01_msb 0 0x226 15:0 r/w cmd_wr_data02_lsb 0 0x228 15:0 r/w cmd_wr_data02_msb 0 0x22a 15:0 r/w cmd_wr_data03_lsb 0 0x22c 15:0 r/w cmd_wr_data03_msb 0 these array registers control the issuing of pm commands. writing to the first location in the array (0x30) causes a new command to be issued to ripp. the command operands are carried in the rest of the registers. cmd_ack: this bit indicates whether a command has been accepted (logic high) or rejected (logic low) by ripp. it is updated by ripp before the cmd_busy is cleared. cmd_code: this is set by the microprocessor to indicate which command is being issued. see table 14 command register encoding for the details. cmd_busy: this bit is set to ?1? internally upon detecting a microprocessor write to this register location; the write indicates that a new command is being issued. after the command is accepted by ripp, ripp clears the bit to ?0? asynchronously to indicate that it is now ready to take the next command. ripp will also update the cmd_ack bit to indicate whether the command has
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 271 been accepted; it puts the return data ? if there is any ? in the command-read data registers. cmd_wr_data00: 8-bit field used to carry the first operand of the current command. see table 14 command register encoding for the details. cmd_wr_data01 ? cmd_wr_data03: 32-bit data fields used to carry the rest of the operands of the current command. see table 14 command register encoding for the details. table 14 command register encoding command cmd_code cmd_wr_data00 cmd_wr_data01 through cmd_wr_data03 add_group 00000 group_tag cmd_wr_data01: tx_phy_valid vector cmd_wr_data02: rx_phy_valid vector cmd_wr_data03: don?t care. delete_group 00001 group_tag don?t care. restart_group 00010 group_tag don?t care. inhibit_group 00100 group_tag don?t care. not_inhibit_gr oup 00101 group_tag don?t care. start_lasr 01000 group_tag cmd_wr_data01: tx_link_vec cmd_wr_data02: rx_link_vec cmd_wr_data03: don?t care. delete_link 01001 group_tag cmd_wr_data01: tx_link_vec cmd_wr_data02: rx_link_vec cmd_wr_data03: don?t care.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 272 command cmd_code cmd_wr_data00 cmd_wr_data01 through cmd_wr_data03 set_rx_phy_d efect 01010 group_tag cmd_wr_data01: don?t care. cmd_wr_data02: rx_link_vec cmd_wr_data03: bit 0: rx link physical defect status (los, lof, ais): ?0?: no defect ?1?: defect exists and needs to be reported to fe. bits 31-1: don?t care.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 273 command cmd_code cmd_wr_data00 cmd_wr_data01 through cmd_wr_data03 unusable_link 01100 group_tag cmd_wr_data01: tx_link_vec cmd_wr_data02: rx_link_vec cmd_wr_data03: bit 6:4: tx_cause. encoding: ?001?: no cause specified ?010?: fault. ?011?: mis-connected ?100?: inhibited ?101?: failed others: reserved (no effect, command void) bit 2:0: rx_cause. encoding: ?001?: no cause specified ?010?: fault. ?011?: mis-connected ?100?: inhibited ?101?: failed others: reserved (no effect, command void) bit 31-7: don?t care.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 274 command cmd_code cmd_wr_data00 cmd_wr_data01 through cmd_wr_data03 update_test_ ptn 10000 group_tag cmd_wr_data01: bit 13: test pattern active indication bit 12:8: lid value of the tx link to be tested. bit 7:0: tx test pattern bit 31-14: don?t care. cmd_wr_data02: don?t care. cmd_wr_data03: don?t care. update_tx_trl 10001 group_tag cmd_wr_data01: bit 4:0: lid value of the tx link to be used as the new trl. bit 31-5: don?t care. cmd_wr_data02: don?t care. cmd_wr_data03: don?t care. read_event 11000 group_tag don?t care. read_delay 11001 group_tag don?t care.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 275 command cmd_code cmd_wr_data00 cmd_wr_data01 through cmd_wr_data03 adjust_delay 11010 group_tag cmd_wr_data01: bit15 : delay_adjust_mode ?0?: remove delay ?1?: add delay bit 9:0: indicates the amount of delay to be added to/removed from a group. bit 31-10: don?t care. cmd_wr_data02: don?t care. cmd_wr_data03: don?t care.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 276 register 0x22e: command read data control register bit type function default 15:2 reserved 0 1:0 r/w cmd_read_data_page_ sel 0 cmd_read_data_page_sel selects which page in the command read data register array is to be made available in the command read data register array. a logic ?0? selects page 0, while a logic ?1? selects page 1 and a logic ?2? selects page 2. the pages may be changed at anytime to enable access to the complete information provided by the read event command. see ?register 0x240-0x02be? for details of the contents of the pages.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 277 register 0x230: icp cell forwarding status register bit type function default 15:1 r reserved 0 0 r2c pm_icp_avl 0 this register serves as the current pm_icp_avl interrupt status. pm_icp_avl: this bit is set by the ripp state machine to indicate that there has been a new icp cell copied over to the icp cell buffer register area. it is cleared upon the microprocessor reading this register location.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 278 register 0x232: icp cell forwarding control register bit type function default 15:2 reserved 0 1 r/w icp_fwd_lock_req 0 r icp_fwd_lock_grant 0 icp_fwd_lock_grant: this bit serves as an access lock bit controlling the access to the forwarding icp buffer. a read from this location returns the current lock status. when the lock bit is set to ?1?, the microprocessor is granted read access to the buffer; further writes by the ripp internal logic are prohibited. otherwise ripp has control over the area. icp_fwd_lock_req: writing ?1? to the register location requests the lock for microprocessor read access; while writing ?0? releases the lock.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 279 register 0x240- 0x2be:ripp command data register array address bit type function default 0x240 15:0 r cmd_data00_lsb 0 0x242 15:0 r cmd_data00_msb 0 0x244 15:0 r cmd_data01_lsb 0 0x246 15:0 r cmd_data01_msb 0 0x248 15:0 r cmd_data02_lsb 0 0x24a 15:0 r cmd_data02_msb 0 0x24c 15:0 r cmd_data03_lsb 0 0x24e 15:0 r cmd_data03_msb 0 0x250 15:0 r cmd_data04_lsb 0 0x252 15:0 r cmd_data04_msb 0 0x254 15:0 r cmd_data05_lsb 0 0x256 15:0 r cmd_data05_msb 0 0x258 15:0 r cmd_data06_lsb 0 0x25a 15:0 r cmd_data06_msb 0 0x25c 15:0 r cmd_data07_lsb 0 0x25e 15:0 r cmd_data07_msb 0 0x260 15:0 r cmd_data08_lsb 0 0x262 15:0 r cmd_data08_msb 0 0x264 15:0 r cmd_data09_lsb 0 0x266 15:0 r cmd_data09_msb 0 0x268 15:0 r cmd_data0a_lsb 0 0x26a 15:0 r cmd_data0a_msb 0 0x26c 15:0 r cmd_data0b_lsb 0 0x26e 15:0 r cmd_data0b_msb 0 0x270 15:0 r cmd_data0c_lsb 0
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 280 address bit type function default 0x272 15:0 r cmd_data0c_msb 0 0x274 15:0 r cmd_data0d_lsb 0 0x276 15:0 r cmd_data0d_msb 0 0x278 15:0 r cmd_data0e_lsb 0 0x27a 15:0 r cmd_data0e_msb 0 0x27c 15:0 r cmd_data0f_lsb 0 0x27e 15:0 r cmd_data0f_msb 0 0x280 15:0 r cmd_data10_lsb 0 0x282 15:0 r cmd_data10_msb 0 0x284 15:0 r cmd_data11_lsb 0 0x286 15:0 r cmd_data11_msb 0 0x288 15:0 r cmd_data12_lsb 0 0x28a 15:0 r cmd_data12_msb 0 0x28c 15:0 r cmd_data13_lsb 0 0x28e 15:0 r cmd_data13_msb 0 0x290 15:0 r cmd_data14_lsb 0 0x292 15:0 r cmd_data14_msb 0 0x294 15:0 r cmd_data15_lsb 0 0x296 15:0 r cmd_data15_msb 0 0x298 15:0 r cmd_data16_lsb 0 0x29a 15:0 r cmd_data16_msb 0 0x29c 15:0 r cmd_data17_lsb 0 0x29e 15:0 r cmd_data17_msb 0 0x2a0 15:0 r cmd_data18_lsb 0 0x2a2 15:0 r cmd_data18_msb 0 0x2a4 15:0 r cmd_data19_lsb 0 0x2a6 15:0 r cmd_data19_msb 0
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 281 address bit type function default 0x2a8 15:0 r cmd_data1a_lsb 0 0x2aa 15:0 r cmd_data1a_msb 0 0x2ac 15:0 r cmd_data1b_lsb 0 0x2ae 15:0 r cmd_data1b_msb 0 0x2b0 15:0 r cmd_data1c_lsb 0 0x2b2 15:0 r cmd_data1c_msb 0 0x2b4 15:0 r cmd_data1d_lsb 0 0x2b6 15:0 r cmd_data1d_msb 0 0x2b8 15:0 r cmd_data1e_lsb 0 0x2ba 15:0 r cmd_data1e_msb 0 0x2bc 15:0 r cmd_data1f_lsb 0 0x2be 15:0 r cmd_data1f_msb 0 the 64 registers in address range 0x240-0x2be serve as a data bank organized as three pages, each with 32 32-bit words. these registers hold the return value from the command. the value of cmd_read_data_page_select determines which page is currently accessible. see table 15 for the details.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 282 table 15 command data register array format command cmd_data00 through cmd_data1f read_event page 0: group interrupt/status. cmd_data00: 32-bit vector where each bit corresponds to a tx lid. a logic ?0? means no interrupt exists on the link, while a logic ?1? means an interrupt does exist on the link. cmd_data01: 32-bit vector where each bit corresponds to an rx link. the vector is organized corresponding to the rx_phy_table in the group configuration record. a logic ?0? means no interrupt exists on the link, while a logic ?1? means an interrupt does exist on the link. cmd_data02: group interrupt/status. see table 16 for bit descriptions. cmd_data03 ? cmd_data1f: don?t care. page 1: link interrupt status. cmd_datan (n = 0x0, ?. 0x1f): see table 17 for bit descriptions. page 2: link status. cmd_datan (n = 0x0, ?. 0x1f): see table 18 for bit descriptions. note that the tx/rx links here are sorted in the same order as in the tx_phy_valid and rx_phy_valid vectors.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 283 command cmd_data00 through cmd_data1f read_delay page 0: cmd_datan (n = 0x0, ?. 0x1f): bit 31-29: don?t care. bit 28: current overrun defect status. bit 27: current lcd defect status. bit 26: current lif defect status. bit 25-23: don?t care. bit 22-21: current ifsm state (ima sync = 2) bit 20-16: don?t care. bit 15:0: dcb write pointer for link n. note that the dcb write pointer should only be considered valid if the attached status bits are 0 and the ifsm state is sync (2). note that the tx/rx links here are sorted in the same order as in the tx_phy_valid and rx_phy_valid vectors. page 1: cmd_data00: bit 15:0: group dcb read pointer. bit 31-16: don?t care. cmd_data01: bit 31:0: current rdat group reader active vector. if no links are active (i.e., all 32 bits are zeros), the group dcb read pointer is invalid. cmd_data02 ? cmd_data1f: don?t care. page 2: don?t care.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 284 table 16 group error/status bit mapping word bit data field description 31:26 reserved reserved group interrupts (10 bit) 25 pm_adjust_dela y_done_int pm adjust_delay procedure done. this means an adjust_delay procedure invoked by the pm command is successfully finished or aborted. 24 fe_trl_int invalid rx trl. this means the fe specified a not-in-group link to be the trl. 23 group_timing_in t group timing mismatch. this means the fe ima transmit clock mode does not mach the ne transmit clock mode. 22 fe_timeou_int startup-ack timeout. the fe fails to transition into the startup-ack state prior to the ne timing out. 21 group_timeout_i nt gsm fails to come out of an insufficient-links state during a group start-up procedure before the relevant timer expires. 20 fe_abort_int fe entered config-aborted state during group start-up. 19 ne_abort_int entered ne config aborted state, fe group parameters unacceptable during group start-up. possible causes are: ima oam label proposed by fe not acceptable. group symmetry proposed by fe not acceptable. rx m proposed by fe not acceptable 18 gtsm_int gtsm state change.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 285 word bit data field description 17 fe_gsm_int fe gsm state change. 16 ne_gsm_int ne gsm state change. group status (10 bit) 15:11 reserved reserved 10 fe_trl_status invalid rx trl. this means the fe specified a not-in-group link to be the trl. 9 group_timing_mi smatch group timing mismatch 8 gtsm gtsm state 7:4 fe_gsm fe gsm state: group state machine state. ?0000?: start-up ?0001?: start-up-ack ?0010?: config-aborted ? unsupported m ?0011?: config-aborted ? incompatible group symmetry ?0100?: config-aborted ? unsupported ima versions ?0101?: reserved ?0110?: reserved ?0111?: config-aborted ? other reasons ?1000?: insufficient-links ?1001?: blocked ?1010?: operational ?1011?-?1111? reserved 3:0 ne_gsm ne gsm state
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 286 table 17 link event interrupt bit mapping word bit data field description rx link error status 31:27 reserved (12 bit) 26 rx_active_int rx lsm transition into/out of active state. 25 idle_cell_int physical layer idle cells were received on the rx link. 24 fe_tx_unusable _int fe tx lsm transitioned into or out of the unusable state. 23 diff_delay_int differential delay is out of bounds on link addition/or recovery. this indicates the delay on the link was out of bounds of the programmed differential delay and that the link failed to come up for this reason. 22 lods_overrun_i nt lods, dcb overrun. an overrun condition occurred. 21 lods_underrun_ int lods, dcb underrun. indicates that the dcb buffer experienced an underrun condition and has disabled itself from forwarding traffic to the atm layer. an underrun occurs when the transport delay for the link is detected to be outside the programmed limit and the transport delay is smaller than the other links within the group in general, this will happen only if the transport delay of the link changes. an underrun condition requires that the link delay be revalidated prior to being placed back in service. 20 lcd_int a change of state of the lcd status bit was detected.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 287 word bit data field description 19 lif_int a change of state of the lif status bit was detected. 18 invalid_icp _int invalid icp parameters detected on rx link during validation of the icp cell parameters causing validation to fail. possible reasons include: invalid lid (i.e., a duplicate). invalid icp cell offset (out of range). invalid rx ima id, which may indicate a misconnectivity problem. invalid oam label received after ima version was determined through negotiation. invalid group symmetry received after symmetry was determined through negotiation. 17 rx_timeout_int indicates the lasr procedure timed out prior to the link entering the active state. 16 reserved reserved tx link error status 15:5 reserved reserved (8 bit) 4 tx_active_int indicates that the ne tx lsm transitioned into/out of active state. 3 fe_rx_unusable _int indicates that fe rx lsm transitioned into/out of unusable state. 2 fe_rx_defect_in t indicates that the fe rx defect indication changed. 1 tx_timeout_int indicates the lasr procedure timed out prior to the link entering the active state. 0 reserved reserved
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 288 table 18 link status bit mapping word bit data field description rx link error status 31 data_playout reserved (15 bit) 30 lods_ovr lods, dcb overrun indicated by rdat. 29 lods_underrun lods, dcb under-run indicated by rdat. 28 lcd lcd, indicated by rdat. 27 lif lif, indicated by rdat. 26:24 fe_tx_lsm fe tx lsm state ?000?: not in group ?001?: unusable ?010?: unusable (fault) ?011?: unusable (mis-connected) ?100? :unusable (inhibited) ?101?: unusable (failed) ?110?: usable ?111?: active 23:21 rx_lsm_icp ne rx lsm state. 20:16 rx_lid rx lid tx link error status 15:8 reserved 7:6 fe_rx_defect fe rx defect (8 bit) 5:3 fe_rx_lsm fe rx lsm state 2:0 tx_lsm_icp ne tx lsm state.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 289 register 0x2c0- 0x2fe: forwarding icp cell buffer address bit type function default 0x2c0 15:0 r icp_word00_lsb 0 0x2c2 15:0 r icp_word00_msb 0 0x2c4 15:0 r icp_word01_lsb 0 0x2c6 15:0 r icp_word01_msb 0 0x2c8 15:0 r icp_word02_lsb 0 0x2ca 15:0 r icp_word02_msb 0 0x2cc 15:0 r icp_word03_lsb 0 0x2ce 15:0 r icp_word03_msb 0 0x2d0 15:0 r icp_word04_lsb 0 0x2d2 15:0 r icp_word04_msb 0 0x2d4 15:0 r icp_word05_lsb 0 0x2d6 15:0 r icp_word05_msb 0 0x2d8 15:0 r icp_word06_lsb 0 0x2da 15:0 r icp_word06_msb 0 0x2dc 15:0 r icp_word07_lsb 0 0x2de 15:0 r icp_word07_msb 0 0x2e0 15:0 r icp_word08_lsb 0 0x2e2 15:0 r icp_word08_msb 0 0x2e4 15:0 r icp_word09_lsb 0 0x2e6 15:0 r icp_word09_msb 0 0x2e8 15:0 r icp_word0a_lsb 0 0x2ea 15:0 r icp_word0a_msb 0 0x2ec 15:0 r icp_word0b_lsb 0 0x2ee 15:0 r icp_word0b_msb 0 0x2f0 15:0 r icp_word0c_lsb 0
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 290 address bit type function default 0x2f2 15:0 r icp_word0c_msb 0 0x2f4 15:0 r icp_word0d_lsb 0 0x2d6 15:0 r icp_word0d_msb 0 0x2f8 15:0 r icp_word0e_lsb 0 0x2fa 15:0 r icp_word0e_msb 0 0x2fc 15:0 r icp_word0f_lsb 0 0x2fe 15:0 r icp_word0f_msb 0 the 32 registers in the address range 0x2a0-0x2de serve as a data bank organized as 16 32-bit words. those words are used to store the icp cell forwarded to pm. see table 19 for the details the format. table 19 receive icp cell buffer structure word bits parameter description octets 6-53 of the payload contained in the last non-errored icp cell for this link. 31:24 23:16 15:8 7:0 0 octet 6 octet 7 octet 8 octet 9 1 octet 10 octet 11 octet 12 octet 13 2 octet 14 octet 15 octet 16 octet 17 3 octet 18 octet 19 octet 20 octet 21 4 octet 22 octet 23 octet 24 octet 25 5 octet 26 octet 27 octet 28 octet 29 6 octet 30 octet 31 octet 32 octet 33 7 octet 34 octet 35 octet 36 octet 37 8 octet 38 octet 39 octet 40 octet 41 9 octet 42 octet 43 octet 44 octet 45 10 octet 46 octet 47 octet 48 octet 49 11 icp_data octet 50 octet 51 octet 52 octet 53
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 291 word bits parameter description 31:1 0 reserved. 9 position_error the current icp cell was received in an unexpected position within the ima frame. if the contents of the cell are valid, then the icp cell is considered valid, but the ifsm will transition to the ima hunt state. 8 header_invali d the atm cell header is not a correct icp cell header. 7 cid_invalid the cell id does not indicate the oam cell type is icp. 6 label_invalid the oam label does not indication ima version 1.1. 5 lid_mm the link identifier in the current icp cell does not match the lid in validation memory. 4 ima_id_mm the ima id in the current icp cell does not match the ima id in validation memory. 3 m_mm the ima frame length in the current icp cell does not match the length in validation memory. 2 seq_error the ima frame sequence number in the current icp cell does not match the sequence number maintained by the rdat. 1 icp_offset_m m the icp cell offset in the current icp cell does not match the offset in validation memory. 12 0 stuff_invalid the link stuff indication in the current icp cell has not progressed properly from the previous value. 13:15 reserved. .
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 292 11.9 rdat registers register 0x300: rdat indirect memory command bit type function default 15 ro mem_busy 0 14 r/w mem_rwb 0 13:4 unused 0 3:0 r/w mem_select 0 writing to this register triggers an indirect memory access to the rdat tables. the indirect memory address (and data register for write operations) must be configured prior to writing the register. mem_select: the indirect memory select indicates the memory table within the rdat which will be accessed. mem_se lect rdat memory table address range 0x00 rdat link statistics memory 0x000-0x14f 0x01 rdat ima group statistics memory 0x000-0x0a7 0x02 rdat tc link statistics memory 0x000-0x0a7 0x03 rdat validation memory 0x000-0x0a7 0x04 rdat link context memory 0x000-0x0a7 0x05 rdat link message status memory 0x000-0x053 0x06-0x07 reserved 0x08 receive icp cell buffer 0x000-0x53f 0x09 rdat ima group context 0x000-0x0a7
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 293 mem_se lect rdat memory table address range memory 0x0a rdat tc link context memory 0x000-0x053 0x0b- 0x0c reserved 0x0d receive atm congestion count register n/a 0x0e- 0x0f reserved mem_rwb: the memory indirect access control bit (mem_rwb) selects between a configure (write) or interrogate (read) access to the rdat internal memory. writing a logic 0 to mem_rwb triggers an indirect write operation. data to be written is taken from the indirect memory data registers. writing a logic 1 to mem_rwb triggers an indirect read operation. the read data can be found in the indirect memory data registers. the address within a memory table can be found in the indirect memory address register. mem_busy: the indirect memory access status bit (mem_busy) reports the progress of an indirect access a write to the indirect memory command register triggers an indirect access and sets the mem_busy bit to a logic 1, mem_busy will remain logic 1 until the access is complete. this register should be polled to determine either: (1) when data from an indirect read operation is available in the indirect memory data registers or (2) when a new indirect write operation may commence.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 294 register 0x302: rdat indirect memory address bit type function default 15:11 unused 0 10:0 r/w mem_addr 0 this register should not be written while the mem_busy bit is set. mem_addr: the indirect memory address indicates the word address within the memory table selected with the mem_select in the command register.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 295 register 0x304: rdat indirect memory data lsb bit type function default 15:0 r/w mem_data_lsb 0 this register should not be written while the mem_busy bit is set. mem_data_lsb: the mem_dat_lsb represents either: (1) the least significant 16 bits of the data to be written to internal memory or (2) the least significant 16 bits of the read data resulting from the previous read operation. the read data is not valid until after the mem_busy bit has been cleared by the rdat. the actual definition of each memory table is described under the indirect memory data msb register description.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 296 register 0x306: rdat indirect memory data msb bit type function default 15:0 r/w mem_data_msb 0 this register should not be written while the mem_busy bit is set. mem_data_msb: the mem_dat_msb represents either: (1) the most significant 16 bits of the data to be written to internal memory or (2) the most significant 16 bits of the read data resulting from the previous read operation. the read data is not valid until after the mem_busy bit has been cleared by the rdat. the actual definition of each memory table is described below.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 297 rdat link statistics memory (mem_select=0) purpose: stores cell and event counts for each physical link. usage: tc links and links in ima groups. each word contains two counts for ima links, one count for tc links. in ima mode, each cell may cause the oif_anomalies count to be incremented, and also may cause one and only one of the other counters to be incremented. in tc mode, each cell will cause one and only one counter to be incremented. all counters roll over unless otherwise noted. maintained by: rdat. record size: four 32-bit words. mem_addr = (physical link number x 4) + word offset table 20 rdat link statistics record (ima) word bits parameter description 0 31:16 stuff_events count of the number of stuff events received on this link. 15:0 oif_anomalies count of the number of times this link has transitioned from the ima sync state to the ima hunt state in the ifsm. 31:16 icp_violations count of hec errored, ocd errored, invalid, or missing icp cells received on this link. this also includes valid icp cells received at unexpected positions. 1 15:0 icp_cells count of the number of valid, non-errored icp cells received on this link. 31:16 filler_cells count of the number of non-errored filler cells received on this link that have been written to the buffer. 2 15:0 user_cells count of the number of user cells received on this link that have been written to the buffer.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 298 word bits parameter description 31:16 filtered_cells count of the cells which were not written to the delay compensation buffer while in the ima enable state (primarily due to errored conditions such as hec errors, filler cells with crc-10 errors, invalid or errored icp cells not at expected positions, overrun, ocd, lcd, oif, lif, , reader not active yet). 3 15:0 dropped_cells count of the number of cells dropped while the link is in ima mode and not enabled. table 21 rdat link statistics record (tc) word parameter description 0 reserved. 1 reserved. 2 user_cells count of the number of user cells received on this link that have been written to the dcb. 3 reserved
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 299 rdat ima group statistics memory (mem_select=1) purpose: stores cell and event counts for each ima group. usage: ima groups only. all counters roll over unless otherwise noted. maintained by: rdat. record size: four 32-bit words. mem_addr = (group tag x 4) + word offset table 22 rdat ima group statistics record word parameter description 0 user_cells count of the number of user cells that have been read from the dcb and transferred to the atm layer for this group. 1 dropped_cells count of the number of cells which have been dropped solely due to atm layer congestion for this group. 2 reserved 3 filler_cells count of the number of filler cells that have been read from the dcb (and not transferred to the atm layer) for this group. buffers that do not contain the correct embedded information will match this criteria. the cell writer may mark cells in this manner for many reasons; for example, when the link is not yet ima enabled.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 300 rdat tc link statistics memory (mem_select=2) purpose: stores cell and event counts for each physical link. usage: tc links only. all counters roll over unless otherwise noted. maintained by: rdat record size: two 32-bit words. mem_addr = (tc tag x 2) + word offset table 23 rdat tc link statistics record word parameter description 0 user_cells count of the number of cells which have been read from the dcb and transferred to the atm layer for this tc link. 1 dropped_cells count of the number of cells which have been dropped solely due to receive cell interface congestion for this tc link.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 301 rdat validation memory (mem_select=3) purpose: contains configuration information for each physical link. used by the rdat to validate incoming icp cells in ima mode, and to control the flow of data to the dcb?s. for tc links, the single bit tc_mode bit must be set. for ima links, this record should be cleared before link addition. usage: ima groups and tc links. maintained by: microprocessor (for tc mode only), ripp. record size: two 32-bit words. mem_addr = (physical link number x 2) + word offset table 24 rdat validation record word bits parameter description 0 31 tc_mode tc_mode controls whether the link is in tc mode or part of an ima group 0 ima link. flow of cells is controlled by the ima protocol and the current ima state 1 tc enabled. cells received for this link are stored in a four-cell fifo in the sdram and scheduled for immediate transmission out the group fifo.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 302 word bits parameter description 30:29 link_sta te link data state. valid only in ima mode. this field reports the current state as set by the ripp to determine how the rdat should handle incoming cells: 00 disabled. cells are read from the link fifos and dropped. 01 ima startup. all icp cells are forwarded to the ripp via the icp fifo, but the ifsm is not started and the delay compensation buffers remain idle for this link. 10 ima monitor. the ifsm is enabled. icp cells are forwarded to the ripp (all during the ifsm hunt state, just cells at the expected icp cell position during the presync and sync states). no cells are written to valid buffer locations in the dcb, but the write pointers are incremented. 11 ima enabled. same as ima monitor, except that user and filler cells are written to the dcb. 28:26 reserved. 25:24 m ima frame length. the value is programmed by the ripp to allow the rdat to perform the ifsm, and to validate the value for m in the incoming icp cells. 00 32 cells 01 64 cells 10 128 cells 11 256 cells. 0 23:16 ima_id ima id. this value is the group identifier, which is programmed by the ripp to allow the rdat to validate this value in the incoming icp cells.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 303 word bits parameter description 15:8 icp_offset icp cell offset. this value is programmed by the ripp to allow the rdat to determine the frame boundary on this link, and to validate this value in the incoming icp cells. 7 reserved. 6 ima_version ima version supported for this link. this will factor into ima oam label checking, if the label_disable bit is not set. 0 = ima version 1.1 1 = ima version 1.0 5 label_disable when set, the ima oam label within the incoming icp cells will not be used for validation of these cells. when not set, the ima oam label must match that specified by the ima_version field. 4:0 lid logical identifier for this link. this value is programmed by the ripp to allow the rdat to validate the incoming icp cells. 31:10 reserved. 1 9:0 dcb_thresh configured overrun threshold of the delay compensation buffer for this link (in cells ? ima only). this must be less than or equal to the value specified in max_dcb_depth in the global configuration register. when this threshold is exceeded (distance between the read and write pointers), the overrun_latch error status will be set. this threshold is programmed by the ripp at link startup.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 304 rdat link context memory (mem_select=4) purpose: contains ima state information for each ima physical link. for ima connections, rdat uses this memory to maintain the ifsm, iesm, osm, and the dcb write pointer for each physical link. note that for all ima links, the group tag must be initialized prior to link addition, with all other fields initialized to zero. for tc links, this memory is used for the external write pointer and should be initialized to zero. usage: ima groups and tc links maintained by: rdat. record size: two 32-bit words. mem_addr = (physical link number x 2) + word offset table 25 rdat link context record word bits parameter description 031 lcd_latch loss of cell delineation defect latched status. this status is maintained by the rdat to report occurrences of lcd on this link. this bit will be set when an lcd defect is detected (as reported in the hec field), and will be cleared by the rdat when a valid icp cell is received. the bit may remain set if the lcd condition persists. 30 overrun_latch dcb overrun latched status. this status is maintained by the rdat to report occurrences of dcb overrun. this bit will be set when a dcb overrun is detected, and will be cleared by the rdat when a valid icp cell is received. the bit may remain set if the overrun condition persists.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 305 word bits parameter description 29 underrun_latch dcb underrun latched status. this status is maintained by the rdat to report occurrences of dcb underrun. this bit will be set when a dcb underrun is detected (by the cell reader process), and will be cleared by the rdat when a valid icp cell is received. the bit may remain set if the underrun condition re-occurs. 28:25 reserved 24:15 reserved 14:13 iesm_state ima error/maintenance state. this state is maintained by the rdat to indicate the current state in the iesm for this link. 11 reserved. 10 ima working. user cells may be written to the dcb. 01 oif anomaly. user cells are replaced with filler cells in the dcb. 00 lif defect. user cells are replaced with filler cells in the dcb. 12:10 oif_cnt count of the number of ima frames while in the out of ima frame (oif) anomaly. this value is compared against gamma + 2 to detect the loss of an ima frame (lif) gamma is set in register 0x308. once the lif condition has been detected, this count is reset, and is used to count the persistence of ima sync for 2 ima frames. 9 last_cell_stuff active high bit indicating when the last cell received on this link was a stuff cell (required for proper ifsm processing). 8:7 reserved.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 306 word bits parameter description 6:0 group_tag the group tag associated with this link. the value is set by the read process; it is used by the cell write process to retrieve the group read pointer, in order to detect overrun conditions. 131 reserved 30 reserved 29 idleerr idle cell received during ima status. this status is maintained by the rdat to report occurrences of idle cells on ima links to pm via the ripp. this bit will be set when an idle cell is detected on an ima link, and will be cleared when the rdat message clear command is issued with the idleerr_clear bit set (indicating that the ripp has acknowledged the problem). 28:26 reserved 25:23 stuff_cnt current link stuff count. this indicates the occurrence of the next stuff event. when an icp cell is received, this count is set to the value in the link stuff indication in that cell. in the event of an errored, invalid, or missing icp cell, the count will be automatically decremented (unless the count is 000 or 111). note that an invalid stuff sequence will be interpreted as an invalid icp cell. 111 no imminent stuff event. 110-101 reserved. 100 stuff event in 4 icp cell locations. 011 stuff event in 3 icp cell locations. 010 stuff event in 2 icp cell locations. 001 stuff event in 1 icp cell locations. 000 the next cell received on this link is a stuff event.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 307 word bits parameter description 22:21 ifsm_state ima frame synchronization mechanism state. this state is maintained by the rdat to indicate the current state in the ifsm for this link. 00 ima hunt. performs a cell-by-cell search for ima framing. cells are not written to the dcb. 01 ima presync. performs a frame-by-frame search for valid icp cells. cells are not written to the dcb (although write pointers are maintained). 10 ima sync. verifies ima framing on a frame-by-frame basis. valid cells are written to the dcb. 11 reserved. 20:18 state_cnt state count. this count is used within the ifsm, and has dual meaning, depending on the state. in the ima presync state, this is the current number of consecutive valid icp cells. this value is compared against the device gamma value to determine when the ifsm may enter the ima sync state from the ima presync state. once the ima sync or hunt state is entered, this value is reset to 0. in the ima sync state, this is the current number of consecutive errored icp cells. this value is compared against the device beta value to determine when the ifsm may enter the ima hunt state from the ima sync state. once the ima hunt state is entered, or a non-errored cell is received, this value is reset to 0. 17:16 invalid_cnt current number of consecutive invalid icp cells. this value is compared against the device alpha value to determine when the ifsm may enter the ima hunt state from the ima sync state. once the ima hunt state is entered, or a valid cell is received, this value is reset to 0, and this value may only be incremented in the ima sync state.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 308 word bits parameter description 15:0 write_ptr current delay compensation buffer write pointer for this link. the least significant portion of the write pointer is the cell number within the ima frame, while the most significant portion represents the ima frame sequence number. the actual number of bits per field depends on the value for m for this link. bits 9:0 for max_dcb_depth = 1024 always represent the actual buffer write pointer (or bits 7:0 for max_dcb_depth = 256). the write pointer is initialized by the rdat when a valid icp cell is received while in the ima hunt state, and is incremented otherwise. the most significant bits (not determined by the frame sequence number) will be synchronized to the group read pointer upper bits. (if the lower portion of the write pointer is less than the lower portion of the read pointer, then the write pointer upper bits will be set to one greater than the read pointer upper bits). each increment of the write pointer represents a single cell time at the link line rate. all write pointers within a group can be compared in order to determine the differential delay.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 309 rdat link message status memory (mem_select=5) purpose: contains the current message status indicator for each physical link. this information is used solely by rdat for communication with the ripp, and should be initialized to zero by pm at link addition. usage: ima groups only. maintained by: rdat. record size: one 32-bit word. mem_addr = physical link number table 26 rdat link message status record bits parameter description 9 msg_status rdat message fifo status. this bit is set by the rdat when a message for this link is written to the rdat message fifo. the bit is cleared when a command for this link is written to the rdat message clear command register. 8 reserved 7:0 reserved
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 310 receive icp cell buffer (mem_select=8) purpose: contains the most recently received non-errored icp cell for each physical link. this record is provided for read access only. usage: ima groups only. maintained by: rdat record size: 16 32-bit words. mem_addr = (physical link number x 16) + word offset table 27 receive icp cell buffer structure word bits parameter description octets 6-53 of the payload contained in the last non-errored icp cell for this link. 31:24 23:16 15:8 7:0 0 octet 6 octet 7 octet 8 octet 9 1 octet 10 octet 11 octet 12 octet 13 2 octet 14 octet 15 octet 16 octet 17 3 octet 18 octet 19 octet 20 octet 21 4 octet 22 octet 23 octet 24 octet 25 5 octet 26 octet 27 octet 28 octet 29 6 octet 30 octet 31 octet 32 octet 33 7 octet 34 octet 35 octet 36 octet 37 8 octet 38 octet 39 octet 40 octet 41 9 octet 42 octet 43 octet 44 octet 45 10 octet 46 octet 47 octet 48 octet 49 11 icp_data octet 50 octet 51 octet 52 octet 53 12 31:10 reserved.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 311 word bits parameter description 9 position_error the current icp cell was received in an unexpected position within the ima frame. if the contents of the cell are valid, then the icp cell is considered valid, but the ifsm will transition to the ima hunt state. 8 header_invalid the atm cell header is not a correct icp cell header. 7 cid_invalid the cell id does not indicate the oam cell type is icp. 6 label_invalid the oam label does not indication ima version 1.1. 5 lid_mm the link identifier in the current icp cell does not match the lid in validation memory. 4 ima_id_mm the ima id in the current icp cell does not match the ima id in validation memory. 3 m_mm the ima frame length in the current icp cell does not match the length in validation memory. 2 seq_error the ima frame sequence number in the current icp cell does not match the sequence number maintained by the rdat. 1 icp_offset_mm the icp cell offset in the current icp cell does not match the offset in validation memory. 0 stuff_invalid the link stuff indication in the current icp cell has not progressed properly from the previous value. 13:15 reserved.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 312 rdat ima group context memory (mem_select=9) purpose: contains state information for each ima group. vphy_id is the only field that must be configured by pm (prior to ima group startup). usage: ima groups only. maintained by: rdat, pm record size: four 32-bit words. mem_addr = (group tag x 4) + word offset table 28 rdat ima group context record word bits parameter description 0 31:16 vphy_id virtual phy id. for multi-channel utopia mode, this identifies which channel in the rxaps fifo cells received for this group will be written to. the least significant 5 bits determine the destination channel of the rxaps fifo for this ima group, and the upper 11-bits are unused. for any-phy mode and single channel utopia, this identifies the address which will be prepended to all cells as they are written to the single channel rxaps fifo. for single channel utopia mode and any-phy mode, the least significant 7 bits must uniquely identify a channel (legal values of 0-83) and the upper 9 bits are user selectable. 15:0 reserved. 1 31:16 reserved
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 313 word bits parameter description 15:0 read_ptr current read pointer for the delay compensation buffers associated with this group. the most significant bits represent an extension of the pointer, which is based on the ima frame sequence number. this field is initialized at link addition using the dcb depth command (with the initiate bit set). 2 31:0 reserved 3 31:0 reserved.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 314 rdat tc link context memory (mem_select=0xa) purpose: contains state information for each tc link. vphy_id is the only field that must be configured. usage: tc links only. maintained by: rdat, microprocessor. record size: one 32-bit word. mem_addr = tc tag table 29 rdat tc link context record bits parameter description 31:16 vphy_id virtual phy id. for utopia l2 multi-address mode, this identifies which channel in the rxaps fifo cells received for this group will be written to. the least significant 5 bits determine the destination channel of the rxaps fifo for this ima group, and the upper 11-bits are unused. for any-phy and utopia l2 single-address modes, this identifies the address which will be prepended to all cells as they are written to the single channel rxaps fifo. for single channel utopia mode and any-phy mode, the least significant 7 bits must uniquely identify a channel (legal values of 0-83) and the upper 9 bits are user selectable. 15:0 read_ptr current read pointer for the delay compensation buffers associated with this tc connection. receive atm congestion count register (mem_select=0xd) purpose: contains a global count of the number of cells dropped due to receive cell interface congestion. rdat increments this counter and sets one of the receive atm congestion status bits each time it drops a cell.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 315 usage: global. maintained by: rdat. record size: one word. mem_addr is not used for accesses to this register. table 30 receive atm congestion count register bits parameter description 31:0 cong_count count of the total number of cells dropped due to atm congestion.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 316 register 0x308: rdat configuration bit type function default 15 r/w rdat_enable 0 14:8 unused 0 7:5 r/w gamma 1 4:2 r/w beta 2 1:0 r/w alpha 2 alpha: alpha represents the number of consecutive invalid icp cells which will cause the ifsm to transition from the ima sync state to the ima hunt state. value definition 0 undefined 1-2 number of consecutive invalid icp cells 3 undefined beta: beta represents the number of consecutive errored icp cells which will cause the ifsm to transition from the ima sync state to the ima hunt state. value definition 0 undefined 1-5 number of consecutive errored icp cells 6-7 undefined gamma: gamma represents the number of consecutive valid icp cells which will allow the ifsm to transition from the ima presync state to the ima sync state. gamma+2 also represents the number of frames the iesm will wait after detecting oif before entering the lif state.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 317 value definition 0 undefined 1-5 number of consecutive valid icp cells 6-7 undefined rdat_enable: when set, this bit enables the rdat state machines. when disabled, the link fifos are not serviced and idcc requests are ignored. the operation of the microprocessor accesses are not affected by this enable.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 318 register 0x30a: receive atm congestion interrupt lsb bit type function default 15:0 r2c cong(15:0) 0 the status in this register is latched, and it is cleared when read. cong(15:0): cong(15:0) is a bit-vector indicating on which channel a cell was dropped at the receive cell interface. in utopia-2 multi-address mode, a set bit indicates that a cell has been dropped on the corresponding channel due to a full rxaps fifo. in any-phy and utopia-2 single address modes, bit 0 set indicates that a cell has been dropped because the single shared rxaps fifo is full, or because 16 cells are already stored in the fifo for the current ima group or tc link. bits 15:1 are unused. read the receive atm congestion count register (mem_select=0xd) to determine the total number of cells dropped.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 319 register 0x30c: receive atm congestion interrupt msb bit type function default 15:0 r2c cong(31:16) 0 the status in this register is latched; it is cleared when read. cong(31:16): cong(31:16) is a bit-vector indicating on which channel a cell was dropped at the receive cell interface. in utopia-2 multi-address mode, a set bit indicates that a cell has been dropped on the corresponding channel due to a full rxaps fifo. bit 31 is unused. in any-phy and utopia-2 single address modes, cong(31:16) is unused. read the receive atm congestion count register (mem_select=0xd) to determine the total number of cells dropped.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 320 register 0x30e: receive tc link fifo overrun interrupt register bit type function default 15:7 unused 0 6:0 r physical_link 0 physical_link: indicates the most recent physical link number that experienced link fifo overrun. physical_link is valid only when tc_overrun=1 in the rdat master interrupt status register. this registers is not used to report overruns on physical links which are allocated to ima groups.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 321 register 0x310: rdat master interrupt register bit type function default 15 ro reserved 0 14:3 unused 0 2 r2c tc_overrun 0 1 ro atm_cong_msb 0 0 ro atm_cong_lsb 0 atm_cong_lsb: when set, this bit indicates that an interrupt bit is set in the receive atm congestion interrupt lsb register. this bit will be clear when no interrupt conditions are present in that register, or when the conditions are not enabled using the receive atm congestion interrupt enable lsb register. atm_cong_msb: when set, this bit indicates that an interrupt bit is set in the receive atm congestion interrupt msb register. this bit will be clear when no interrupt conditions are present in that register, or when the conditions are not enabled using the receive atm congestion interrupt enable msb register. tc_overrun: when set, this bit indicates that a link fifo overrun has occurred on the physical link indicated in the tc overrun status register. note that link fifo overrun will occur only if the setup procedures are not followed properly by pm. this bit is not used to report overruns on physical links which are allocated to ima groups. this bit will clear when this register is read.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 322 register 0x312: receive atm congestion interrupt enable lsb bit type function default 15:0 r/w cong_intr_en(15:0 ) 0x0000 cong_intr_en(15:0): the cong_intr_en vector enables the atm fifo congestion status for rdat_intr interrupt generation. when a bit is a one, the associated status will generate an interrupt.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 323 register 0x314: receive atm congestion interrupt enable msb bit type function default 15:0 r/w cong_intr_en(31:1 6) 0x0000 cong_intr_en(31:16): the cong_intr_en vector enables the atm fifo congestion status for rdat_intr interrupt generation. when a bit is a one, the associated status will generate an interrupt.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 324 register 0x316: rdat master interrupt enable bit type function default 15 r/w 0 14:3 unused 0 2 r/w overrun_intr_en 0 1 r/w cong_msb_intr_e n 0 0 r/w cong_lsb_intr_e n 0 cong_lsb_intr_en: when set to a one, the cong_lsb_intr_en allows the presence of an enabled interrupt in the atm congestion status lsb register to cause an rdat interrupt. cong_msb_intr_en: when set to a one, the cong_msb_intr_en allows the presence of an enabled interrupt in the atm congestion status msb register to cause an rdat interrupt. overrun_intr_en: the overrun_intr_en bit enables the tc overrun status for rdat_intr interrupt generation. when the enable bit is a one, a tc overrun will generate an interrupt.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 325 11.10 tima registers register 0x320: tima indirect memory command bit type function default 15 r mem_busy 0 14 r/w mem_rwb 0 13:3 unused 0 2:0 r/w mem_select 0 writing to this register triggers an indirect memory access to the tima context tables. the indirect memory address (and data register for write operations) must be configured prior to writing this register. mem_select: the indirect memory select indicates the memory table (or register bank) within the tima which will be accessed. mem_select tima memory address range 0 transmit ima group context tab le 0-671 (29fhex) 0 transmit ima group configuration table 672 ? 713 (2a0 ? 2c9 hex) 1 transmit lid to physical link mapping table 0-1343 (53f hex) 2 transmit physical link context tab le 0- 167(a7 hex) 3-7 reserved
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 326 mem_rwb: the memory indirect access control bit (mem_rwb) selects between a configure (write) or interrogate (read) access to the tima internal. writing a logic 0 to mem_rwb triggers an indirect write operation. data to be written is taken from the indirect memory data registers. writing a logic 1 to mem_rwb triggers an indirect read operation. the read data can be found in the indirect memory data registers. the address within a memory table can be found in the indirect memory address register. mem_busy: the indirect memory access status bit (mem_busy) reports the progress of an indirect access. a write to the indirect memory command register triggers an indirect access and sets mem_busy to a logic 1; mem_busy will remain logic 1 until the access is complete. this register should be polled to determine when data from an indirect read operation is available in the tima indirect memory data registers or to determine when a new indirect write operation may commence.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 327 register 0x322: tima indirect memory address bit type function default 15:11 unused 0 10:0 r/w mem_addr 0 this register provides the address for indirect memory access to the tima context tables.. mem_addr: the indirect memory address indicates the word address within the memory table selected with the mem_select in the tima indirect memory command register.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 328 register 0x324: tima indirect memory data lsb bit type function default 15:0 r/w mem_data_lsb 0 this register should not be written while the mem_busy bit is set. mem_data_lsb: the mem_data_lsb represents either: (1) the least significant 16 bits of the data to be written to internal memory or (2) the least significant 16 bits of the read data resulting from the previous read operation. the read data is not valid until after the mem_busy bit has been cleared by the tima. the actual definition of each memory table is described under tima indirect memory data msb. if a memory location is read which does not support any bits of 15:0, then the corresponding register bit is loaded with 0. if a memory location is written which does not support bits 15:0, then the data in the corresponding register bit is ignored.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 329 register 0x326: tima indirect memory data msb bit type function default 15:0 r/w mem_data_msb 0 this register should not be written while the mem_busy bit is set. mem_data_msb: the mem_data_msb represents either: (1) the most significant 16 bits (31:16) of the data to be written to internal memory or (2) the most significant bits of the data resulting from the previous read operation. the read data is not valid until after the mem_busy bit has been cleared by the tima. if a memory location is read which does not support bits 31:16, then corresponding register bits are loaded with 0. if a memory location is written which does not support bits 31:16, then data in the corresponding register bits is ignored. note that a write operation will corrupt the read data. the actual definition of each memory table is described below:
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 330 transmit ima group context table (mem_select=0) purpose: contains state information, statistics, and icp cell information (delivered by the ripp) for each ima group. usage: ima groups only. maintained by: tima. record size: 16 32-bit words. mem_addr = (group tag x 16) + word offset table 31 transmit ima group context record word bits parameter description 0 31:0 reserved. 1 31:16 discarded cells number of cells discarded from atm layer when the ima group was in an non- operational state. 15:0 reserved 2 31:0 number of cell per group continuously running cell count of all atm cells read from the associated group fifo and sent to link fifos.. maintained by tima state machine.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 331 word bits parameter description 3 31:0 number of atm filler cells continuously running cell count of atm filler cells (generated when there is no atm cell to send) delivered on all links in the group. maintained by tima state machine. 4 31:0 reserved 31:24 reserved 23:16 icp octet 11 15:8 icp octet 12 5 7:0 icp octet 13 6 31:0 icp octet 14 icp octet 15 icp octet 16 icp octet 17 7 31:0 icp octet 18 icp octet 19 icp octet 20 icp octet 21 8 31:0 icp octet 22 icp octet 23 icp octet 24 icp octet 25 9 31:0 icp octet 26 icp octet 27 icp octet 28 icp octet 29 icp cell octets that are maintained by ripp and placed into the outgoing icp cells for all links in the group.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 332 word bits parameter description 10 31:0 icp octet 30 icp octet 31 icp octet 32 icp octet 33 11 31:0 icp octet 34 icp octet 35 icp octet 36 icp octet 37 12 31:0 icp octet 38 icp octet 39 icp octet 40 icp octet 41 13 31:0 icp octet 42 icp octet 43 icp octet 44 icp octet 45 14 31:0 icp octet 46 icp octet 47 icp octet 48 icp octet 49 31:24 icp octet 50 23:16 icp octet 51 15 15:0 reserved
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 333 transmit ima group configuration table (mem_select=0) purpose: contains ima configuration data programmed by pm. usage: ima groups only. maintained by: microprocessor. record size: one 32-bit word. mem_addr = 0x2a0 + group tag table 32 transmit ima group configuration table record bits parameter description 31:23 unused 22:16 vphy address vphy address (group fifo number) which is assigned to this group. this field should be modified by pm only during group configuration. valid values are 0 to 83. 15:9 unused 10 disable cell discard configuration bit which determines if the atm cell discarding feature is enabled for this ima group. when set to 0, atm cells will be read and discarded from the group fifo (one for each request) if there are no active links in the group. when set to 1, cell discarding will not occur for the group. 9stuff advertise mode configuration bit which determines whether stuff cell advertising is done either four icp cells ahead or one icp cell ahead of the stuff event. this bit should be changed only on group startup, otherwise the number of cells between trl stuff events will not be correct. 0 = one icp cell ahead; 1 = four icp cells ahead 8 stuff mode configuration bit which determines whether itc or ctc stuff mode is actually used for this group. note it is possible to advertise itc transmit clock mode in an
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 334 icp cell but still use a common clock and ctc stuff mode. 0 = itc stuff mode, 1 = ctc stuff mode 7:0 oam label static field to be inserted into octet 6 of icp cells and oam cells.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 335 transmit-lid-to-physical-link mapping table (mem_select=1) purpose: maps physical links to ima groups. usage: ima groups only. maintained by: microprocessor. organization: a single linear table containing 1344(42 x32) 7-bit entries. each entry is addressed by using the group tag concatenated with the link id (lid). each physical link id is stored as a 7-bit value. in general, this table is sparsely populated since each of the 84 physical link tags can exist in only one table entry. mem_addr = (group tag x 32) + lid value table 33 transmit lid to physical link mapping table bits description 6:0 physical link for corresponding group tag and link id. only values 0 to 83 are valid for this field.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 336 transmit physical link context table (mem_select=2) purpose: contains state information and statistics for each tc link or ima link. each record is addressed by either the tc tag from the idcc or the physical link tag from the transmit-lid-to-physical-link mapping table. usage: ima groups and tc links. maintained by: tima and microprocessor. record size: two 32-bit words. mem_addr = (physical link tag or tc tag x 2) + word offset table 34 tima physical link context record word bits parameter description 31:24 unused unused 23:16 icp offset or tc mode vphy address ima mode : this field is indexed by the physical link tag and is used to determine the cell count within a frame at which an icp is to be inserted for the link. the width of the field used by the tima is dependent on the value of m used for the particular group and is shown in the following: m=256 icp offset determined by bits [23:16] m=128 icp offset determined by bits [23:17] m=64 icp offset determined by bits [23:18] m=32 icp offset determined by bits [23:19] the mapping of the icp offset is set such that the offset should not have to be changed if m is changed. values 0 to 255 are valid. tc mode : this field is indexed by the tc tag delivered by the idcc and is used to determine the vphy atm source fifo associated with the tc connection. only values 0 to 83 are valid. 0 15:9 reserved
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 337 word bits parameter description 8:6 startup cell count cell count used to track the first four cells sent into each link fifo after startup. used to inhibit cell reads from the link fifo until four cells have been written into the link fifo so that the nominal 4 to 5 cell depth can be achieved. this field must be initialized to four by pm before the link is enabled to ensure proper startup. however, if the link is to be used for either a low speed or high speed tc mode connection, this field must be initialized to a value of 0 to prevent any read inhibit. 5:0 reserved . 1 31:16 ima mode stuff event count or tc mode user cell count (upper word) ) ima mode : this field is indexed by the physical link tag and is used to store a continuously running count of the number of stuff events inserted on the link. it is maintained by the transmit engine and is read by the pm. this field should only be reset when the link is not enabled. tc mode : this field is indexed by the tc tag delivered by the idcc and is used to store the upper 16-bit word of a continuously running 32- bit count of the total number of atm user cells sent on the link. it is maintained by the transmit engine and is read by the pm. this field should only be reset when the link is not enabled.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 338 word bits parameter description 15:0 ima mode total user cell count or tc mode user cell count (lower word) ) ima mode : this field is indexed by the physical link tag and is used to store a continuously running count of the number atm user cells transferred on the link. it is maintained by the transmit engine and is read by the pm. this field should only be reset when the link is not enabled. tc mode : this field is indexed by the tc tag delivered by the idcc and is used to store the lower 16-bit word of a continuously running 32-bit count of the total number of atm user cells sent on the link. it is maintained by the transmit engine and is read by the pm. this field should only be reset when the link is not enabled.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 339 register 0x328-0x332 transmit link fifo overrun interrupt register address bit type function default 0x328 15:0 r2c link_fifo_overflow_st at [15:0] 0 0x32a 15:0 r2c link_fifo_overflow_st at [31:16] 0 0x32c 15:0 r2c link_fifo_overflow_st at [47:32] 0 0x32e 15:0 r2c link_fifo_overflow_st at [63:48] 0 0x330 15:0 r2c link_fifo_overflow_st at [79:64] 0 15:4 unused 0x332 3:0 r2c link_fifo_overflow_st at [83:80] 0 the transmit link fifo overrun interrupt register reports an overrun on the ttc link fifos, which occurs when a write is attempted to a full fifo. these interrupts should not occur during normal operation, and indicate either a configuration error or a loss of clock on a non-trl link of an ima group.. if an overrun occurs during the same cycle as a read, the set of an interrupt bit overrides the clear operation. link fifo overflow status[83:0] on read, each bit reports the status of the corresponding link fifo (1= overflow, 0 = no overflow). each set overflow status bit is cleared after a read.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 340 register 0x336 interrupt enable bit type function default 15:1 r reserved 0 0 r/w link fifo overflow interrupt enable 0 the interrupt enable bits control whether the corresponding interrupt source will cause an interrupt on the intb output or will be masked. link fifo overflow interrupt enable 1) link fifo overflow interrupts will be enabled. 0) link fifo overflow interrupts are not enabled.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 341 11.11 tx idcc registers register 0x340: txidcc indirect link control register bit type function default 15 r cbusy 0 14 r/w lrwb 0 13:9 n/a unused n/a 8:7 r/w lsel[1:0] 0 6:0 r/w laddr[6:0] 0 writing to this register triggers an indirect channel register access. laddr [6:0]: the indirect link address number (laddr [6:0]) indicates the link to be configured or interrogated in the indirect link access. lsel: lsel selects the ram to interrogate or configure. 00 ? unused 01 ? link table 10 ? reserved 11 ? reserved lrwb: the link indirect access control bit (lrwb) selects between a configure (write) or interrogate (read) access to the ram. writing logic 0 to lrwb triggers an indirect write operation. data to be written is taken from the indirect link data registers. writing logic 1 to lrwb triggers an indirect read operation. cbusy: the indirect access command bit (cbusy) reports the progress of an indirect access. cbusy is set high to trigger an indirect access; it will stay high until the access is complete. once the access is complete, the cbusy signal is
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 342 reset by the device. this register should be polled to determine either: (1) when data from an indirect read operation is available in the indirect data register or (2) when a new indirect write operation may commence.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 343 register 0x342: txidcc indirect link data register bit type function default 15:8 n/a unused n/a 7r/w tc mode 0 6:0 r/w reserved 0
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 344 tc mode:
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 345 if this bit is set, the associated link is in pass-through mode. here, the trl
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 346
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 347 11.12 rx idcc registers register 0x350: rxidcc indirect link control register bit type function default 15 r cbusy 0 14 r/w lrwb 0 13:9 n/a unused n/a 8:7 r/w lsel[1:0] 0 6:0 r/w laddr[6:0] 0 writing to this register triggers an indirect channel register access. laddr [6:0]: the indirect link address number (laddr [6:0]) indicates the link to be configured or interrogated in the indirect link access. lsel: lsel selects the ram to interrogate or configure. 00 ? unused 01 ? link table 10 ? reserved 11 ? reserved lrwb: the link indirect access control bit (lrwb) selects between a configure (write) or interrogate (read) access to the ram. writing logic 0 to lrwb triggers an indirect write operation. data to be written is taken from the indirect link data registers. writing logic 1 to lrwb triggers an indirect read operation. cbusy: the indirect access command bit (cbusy) reports the progress of an indirect access. cbusy is set high to trigger an indirect access, and will stay high until the access is complete. once the access is complete, the cbusy signal
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 348 is reset by the device. this register should be polled to determine when data from an indirect read operation is available in the indirect data register or to determine when a new indirect write operation may commence.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 349 register 0x352: rxidcc indirect link data register bit type function default 15:8 n/a unused n/a 7r/w tc mode 0 6:0 r/w reserved 0 tc mode: if this bit is set, the associated link is in pass through mode. here, the trl and the group tag are don?t care values.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 350 register 0x366: dll status register bit type function default 15:1 r reserved x 0 r run 0 the dll control status register provides information of the dll operation. run: the dll lock status register bit (run) indicates the dll has locked. after system reset, run is logic zero until the dll has locked. for proper operation the dll must be indicate run. the run register bit is cleared only by a system reset .
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 351 12 operation 12.1 hardware configuration the s/uni-ima-84 can be configured in two different modes: clk/data interface or sbi interface. the s/uni-ima-84 is powered up with both modes disabled. the any-phy/utopia interface can also be set up in different modes.. the any- phy/utopia interface will remain tri-state until configured and the respective ra_enable/ta_enable bits are set. 12.2 start-up the s/uni-ima-84 uses an internal dll on sysclk to maintain low skew on the external sdram interface. when the chip is taken out of hardware reset, the dll will go into hunt mode and will adjust the internal sysclk until it aligns with the external sysclk. the microprocessor should poll the run bit in dll control status register until this bit is set. at this point the entire chip with the exception of the microprocessor interface and the dll are in reset. before any configuration can be done, including accessing the ram, the chip must be taken out of software reset by clearing the reset bit in the global reset register. once taken out of reset, the internal ram reset procedure is automatically initiated. the microprocessor should poll the bist_done bit in the global reset register to determine when the internal ram reset is complete. while the internal ram is initializing, access to all internal rams is prohibited, and accesses attempted during this period of time are ignored. once the chip is taken out of reset, the external sdram should be cleared to all zeros to ensure no false crc errors are reported. access to the sdram is through the sdram diagnostic access port as discribed in 12.6.1. at this point, the any-phy/utopia interface is disabled and all any-phy/utopia outputs are tri-stated. also, the line side interfaces are disabled and all internal registers are in their reset state.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 352 12.3 configuring the s/uni-ima-84 12.3.1 configuring sbi interface in sbi mode the following items need to be properly configured: ? the spe type for each of the 3 sbi spes ? spe type can be e1, t1, or ds3 and is configured by setting spen_typ bits in the sbi bus configuration register (sbi_bus_cfg_reg) to the appropriate value. all spes_typ are default to t1 type. ? each spe must be enabled or disabled by writing appropriate value into spen_enbl bit in the sbi bus configuration register. all spes default to being disabled. ? set the proper operation mode by writing 0x0080 to the sbi extract master interrupt status register ? tributary type for each tributary. ? the tributary type must be configured to be framed without cas. this is configured by setting trib_typ to ?01b? in the extract/insert. tributary control register inside the insbi/exsbi for that tributary. the trib_typ default value of ?00b? is not supported ? a tributary can float or be locked to the sbi frame structure. only floating tributaries are supported ? sbi error checking and reporting ? the following errors can be detected on a per link basis: fifo overrun, fifo underrun, and sbi parity error. these all can be enabled/disabled in the insert/extract control register. these errors result in either the sbi_drop_intr or sbi_add_intr output being set. ? parity detection is done only on the drop bus, which is done by the exsbi block. parity can be configured to be odd or even, and it is default to be odd parity.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 353 ? fifo overrun/underrun errors are reported by indicating error status in the extract/insert fifo underrun/overrun interrupt status register with the failing link identified. ? these interrupts can only be cleared by reading the fifo overrun/underrun register with the failing link. only one error can be reported at a time. however errors are latched internally so that if multiple errors occur, any pending errors will be reported when the first one is cleared. ? if the alm bit in the sbi v4 byte is detected to be changed on a particular tributary, then the corresponding spex_alrm_int bit is set in the sbi extract alarm interrupt register. the spex_alrm_stat bit associated with that tributary indicates the current state of the extract sbi alarm on the sbi tributary. this sbi_alrm_intn interrupt can be cleared only by reading the sbi extract alarm interrupt register. 12.3.1.1 programming sequence for sbi ? to have a clean start up, the following programming sequences are recommended when setting up the sbi interface: ? general rules: ? all insbi/exsbi read and write accesses must wait until the bistinit_done bit is set after chip sw_reset is cleared, to allow time for the insbi/exsbi to complete self-initialization. other general control register outside of insbi/exsbi can be configured at any time. ? at initialization, on the sbi drop bus, the sbi tributary receiver should be enabled before the corresponding sbi tributary transmitter (i.e., configuring exsbi before insbi). the same applies for the sbi add bus. ? following a configuration change, which generates a configuration reset, a tributary may not become active for up to 1 ms following the change. ? any write to a tributary control register for a tributary will generate a configuration reset on that tributary, irrespective of whether the data written to the tributary control register is unchanged from the previous value.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 354 ? if dc_en is disabled and an overrun/underrun condition is reported for a link, the link should be reset by writing to the tributary control register for the tributary corresponding to that link. if dc_en is set, then the tributary will automatically be reset. ? insbi/exsbi programming steps: 1. for each write access, wait until the busy bit in the insert/extract tributary ram indirect access control register is clear. note that the busy bit might not be ready for up to 4.32 us after a control ram access. 2. once the busy bit is clear, write to the insert/extract tributary ram indirect access address register specifying the spe and tributary that is about to be configured. 3. then write into the extract tributary control ram indirect access data register to specify the desired control values for that tributary. 4. next, write into the extract tributary ram indirect access control register to specify whether this is to be a write or a read access, by clearing or setting the wrb bit in this register. the above 4 steps must be done and must be repeated for every tributary access. ? tributary configuration sequences: ? configure all the control ram in both exsbi and insbi, following the above four steps. ? enable the spes last by setting the spen_enbl bits in the sbi_bus_cfg_reg. 12.3.2 configuring clock/data interface the clock/data interface has 2 major modes, channelized for e1/t1 traffic and unchannelized for other traffic types. each link should be configured for channelized/unchannelized mode using the rcas/tcas link configuration registers. if configuring channelized links, the t1/e1 mode should be configured at the same time.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 355 one configured, the links are still disabled. the links must be mapped and provisioned (enabled) 12.3.2.1 channelized when channelized links are chosen, the rcas/tcas framing bit threshold must be configured to detect the gap in the clock for the framing bit/byte. this value is dependent upon frame type t1/e1, serial clock speed and refclk frequency. the link disable feature may be used when configuring a link to squelch all data from a link while it is being provisioned. for the tx direction, the data sent in idle timeslots may be selected with the tcas idle time-slot fill data. for t1, all timeslots are used to carry the atm cell data so all timeslots should be mapped to the same virtual link. a one-to-one mapping between physical links and virtual links is recommended. for e1, timeslots 0 and 16 are used for signaling data and do not contain atm cell data. therefore, timeslots 1-15 and 17-31 must be mapped and provisioned (enabled) to carry atm cell data. all of the timeslots in a link should be mapped to the same virtual link. a one-to-one mapping between physical links and virtual links is recommended. for fractional links, multiple fractional atm flows may exist on the same physical link. each flow should be mapped to a unique virtual link. there is a limit of 84 virtual links for the s/uni-ima-84. 12.3.2.2 unchannelized unchannelized is usually used for data streams that are not either t1 or e1 framed. when using the unchannelized interface, the user is responsible for providing a clock which has all framing or overhead bits gapped out. the s/uni- ima-84 receives/sources one bit of data for each clock pulse. the unchannelized mode allows a wider range of clock frequencies. as the serial line frequency increases, the number of links supported decreases. 12.3.2.3 rules for chosing clock frequencies sysclk(min) = max((50mhz * line throughput(mbps)/130 mbps), refclk)
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 356 refclk(min)= + period clock line numlines freq clock line lines num . . * 4 3 4 * 14 , 6 . . * . max 4 3 * 14 . . . * 4 . max ? period refclk period clock line lines num table 35 refclk/sysclk frequency requirement serial frequency # links refclk frequency sysclk frequency 1.544 mhz 32 33 mhz 33 mhz 2.048 mhz 32 33 mhz 33mhz 2.304 mhz 32 33 mhz 33 mhz 8 mhz 8 52 mhz 52mhz 12.3.3 configuring tc layer options tc layer options in the transmit direction include scrambling and hec generations. scrambling should be set as required by the physical layer. tc layer options in the receive direction include descrambling, and interrupt reporting and error handling options. to properly support ima applications, the tc layer functions should not filter out errored cells but pass them to the ima- layer and let the ima-layer filter them out. the options lcdocdpass, hcspass and unasspass should be set for ima applications. if these options are set for tc links, only the unassigned cells will not be filtered by the ima- layer. when running ima, there should never be any idle cells. if idle cells exist on an ima link, it depends upon where the idle cells were inserted whether idlepass is desired to be set. if the idle cells were incorrectly inserted by the tc layer, correct operation could be preserved in the face of errors if idlepass is not set. if the idle cells are inserted by the link layer, correct operation may be preserved by setting idlepass.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 357 the configuration options are programmed one link at a time by following the steps below: ? rttc/tttc programming steps: 1. for each write access, wait until the lbusy bit in the rttc/tttc indirect status register is clear. note that the lbusy bit might not be ready for up to 86 refclk cycle after an access. 2. once the busy bit is clear, write to the rttc/tttc link data register to specify the desired configuration options for that link. 3. next, write into the rttc/tttc indirect status register specifying the spe and link that is about to be configured and whether this is to be a write or a read access, by clearing or setting the lwrb bit in this register. 12.3.4 utopia interface configuration there is very little setup required to configure the any-phy/utopia interface. for typical operation, the following registers need to be written to select the mode of operation and the predefined address or address range of the s/un-ima-84 and the number of active ports of the s/uni-ima-84. ? transmit any-phy/utopia cell available enable ? receive utopia cell available enable ? transmit any-phy address config register ? receive any-phy/utopia config register ? transmit any-phy/utopia config register once the registers are written with the proper configuration information, the enable bit should be set to enable normal operation.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 358 12.4 ima_layer configuration 12.4.1 indirect access to internal memory tables the ima-layer operations are configured by internal memory tables. the access to these tables is by indirect access. the following procedure applies for the indirect accesses in the ripp, rdat, tima, txidcc, and rxidcc blocks. 12.4.1.1 write accesses the indirect write access procedure is as follows: 1) wait until the ?busy? bit in the block indirect memory access control register is clear. 2) once the busy bit is clear, write to the block data indirect data register(s) to specify the data to be written for that link. 3) next, write into the block indirect memory address register specifying the address that is about to be configured and then write block indirect memory command register to specify the table to be accessed and whether the access is to be a write or a read access, by clearing or setting the rwb bit in this register. note that is some instances, the block indirect memory address register is combined with the block indirect memory access control register 12.4.1.2 read accesses the indirect read access procedure is as follows: 1) wait until the ?busy? bit in the block indirect memory access control register is clear. 2) once the busy bit is clear, write into the block indirect memory address register specifying the address that is about to be configured and then write block indirect memory command register to specify the table to be accessed and whether the access is to be a write or a read access, by clearing or setting the rwb bit in this register. note that is some instances, the block indirect memory address register is combined with the block indirect memory access control register
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 359 3) poll the ?busy? bit in the block indirect memory access control until it is cleared. 4)read returned data from the block data indirect data register(s). 12.4.2 configuring links for transmission convergence operations after all of the interfaces have been configured, in order to configure a link for atm over t1/e1, the mapping from physical link to any-phy/utopia address must be set and the link must be set to tc mode within the ima sublayer. also, all link based statistics should be cleared. for tc only links, all ripp tables are not used and should not be programmed. 12.4.2.1 transmitter to map the physical link to a any-phy/utopia address, the vphy address field must be programmed in the tima physical link context record for the physical link. all other fields in this table should be cleared to zero. this table may be accessed by the tima indirect memory access registers. to put the physical link into tc mode set the tc_mode bit in the txidcc. this bit may be accessed by the txidcc indirect memory access registers. 12.4.2.2 receiver to map the physical link to an any-phy/utopia address, the vphy address field must be programmed in the rdat tc context record for the physical link. all other fields in this table should be cleared to zero. this table may be accessed by the rdat indirect memory access registers. the rdat link statistics record, the rdat tc group statistics record, the rdat link context record should also be cleared to zero to reset the statistic counts. the rdat validation record should be set to tc_mode. to put the physical link into tc mode, set the tc_mode bit in the rxidcc. this bit may be accessed by the rxidcc indirect memory access registers. note: to successfully configure a ds3 connection, the configuration must be done prior to enabling the data flow. this can be done by configuring the rdat prior to setting the exsbi trib_enbl bit and setting the spen_enbl bit.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 360 set the rdat_en bit in the rdat configuration register. 12.4.2.3 removing links from transmission convergence operations to disable a link in tc mode in the transmitter, the tc_mode bit in the txidcc must be cleared. to disable a link in tc mode in the receiver, first the rdat validation record should be cleared, then the tc_mode bit in the rxidcc must be cleared. this sequence will ensure that transient interrupts are not generated.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 361 12.4.3 configuring for ima operations all ima timeouts are programmable. in general, the default values result in ~1 sec timeouts with a 55 mhz sysclk. the global ima interrupt enables default to disabled. in an interrupt driven system, these interrupt should be selectively enabled in registers 0x218, 0x21a, and 0x21c. ripp_en in register ?x200 controls whether internal ima state machines engine is enabled. this must be set for proper operation. ima groups are configured using the following per group tables: ? ripp group configuration record : group options and configuration, ? tima tx-lid-to-physcial-link mapping table: maps group tag/lid to physical link. ? tima tx group configuration record : maps group to any-phy/utopia port id, sets stuffing mode and oam label. ? rdat ima group context record : maps group to any-phy/utopia port id and also the following per link tables: ? ripp tx link configuration record : maps physical link to group tag/lid, enables tx link interrupts. ? ripp rx link configuration record : maps physical link to group tag, enables rx link interrupts ? tima tx physical link context record: sets icp offset. ? rdat link context record : maps physical link to group. 12.4.3.1 configuring a group for ima ima groups within the s/uni-ima-84 are identified by a ?group tag?. the group tag is an identifier with values from 0 to 41 that uniquely identifies the group for
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 362 programming and reporting purposes within the s/uni-ima-84. the group tag is completely independent of the group id located within the icp cells. once a group tag is chosen for a group, the following records need to be programmed for the group: ripp group configuration record : initial group options and configuration, after the group is started, the following configuration options may be changed only with a ripp command or in conjunction with a group restart. expected oam label group symmetry ima 1.1 versus ima 1.0 ima id m expected clk mode (itc/ctc) the following entries within the ripp group configuration record may be changed without a group restart of ripp command. when changing these fields, care must be taken not to change other fields. minimum # of links differential delay tolerance and options per group interrupt enables rx physical links that are in the group tx lid to link mapping table : select the lids to be used by the tx links and program the physical links into the appropriate group tag/lid locations. tima group configuration record : tx vphy id stuff advertise mode
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 363 actual stuffing mode(itc/ctc) used transmitted oam label. rdat ima group context record rx vphy id also, while configuring a group, the context records that contain statistics should be initialized. the following records should be initialized to zero: ripp group context record, rdat ima group statistics record, tima group context record. 12.4.3.2 configuring a link for ima all link-based records are indexed by the physical link id. prior to configuring a link, the user should check to ensure that it is not in use already. this is necessary since link deletion from a group may take some time due to the necessity of allowing the dcb buffer for the link to drain. reading the rx_enable bit in the ripp rx link context record and the tx_enable bit in the ripp tx link context record can check this. the following fields in the following records need to be programmed; other fields in the records should be cleared to zero. ripp tx link configuration record tx_lid group tag per link interrupt enables ripp rx link configuration record group tag per link interrupt enables
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 364 tima physical link context record icp offset startup cell count = b?100 rdat link context record group tag also, while configuring a link, the context records that contain statistics and assorted context should be initialized to zero. the following records should be initialized to zero: ripp tx link context record, ripp rx link context record, rdat link statistics record, rdat link validation record rxidcc link data txidcc link data in addition, the msg_status bit in the rdat link message status record must be cleared using a read-modify-write operation. the other bits in the record contain link specific internal context which must be maintained. there will be no contention for this memory between pm and the rdat if the operation is performed while the link is not enabled for tc or ima operation.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 365 12.5 ima operations ima operations are controlled via commands issued to the ripp (receive ima protocol processor). in general, once started, the ripp performs the hand shaking of state transitions between the near-end and far-end of an ima connection. 12.5.1 issuing a ripp command the ripp commands control the lsm and gsm state machines. the group is identified by the group tag and the links involved are identified with a 32-bit vector. the tx_link_vec has one bit for each tx lid and bit 0 indicates tx lid 0 and bit 31 indicates tx lid31. for symmetrical operations, the rx lids are not known until the icp cells from a link are validated. the user controls the relationship between physical links and the rx link vector through the rx physical link table in the ripp group configuration record. the rx physical link table should be configured according to the tx lid values. for example, the physical link id for the link with tx lid = 0 should be programmed as the rx physical link 0. when using the ripp commands, the physical link entered for rx physical link 0 will be controlled by bit 0 of the rx_link_vec and the physical link entered for rx physical link 31 in the table will be controlled by bit 31 of the rx_link_vec. for asymmetric operations, since there is not a tx link for each possible rx link and the rx lids are not known until the icp cells from a link are validated, the user controls the relationship between physical links and the rx link vector through the rx physical link table in the ripp group configuration record. there are no restrictions on how this table should be configured in asymmetrical mode. the contents of the rx_phy_table do not depend on lid values. when using the ripp commands, the physical link entered for rx physical link 0 will be controlled by bit 0 of the rx_link_vec and the physical link entered for rx physical link 31 in the table will be controlled by bit 31 of the rx_link_vec. the ripp command procedure is as follows: 1) wait until the ?cmd_busy? bit in the ripp command register is clear. 2) once the cmd_busy bit is clear, write the necessary data for the command registers 0x222 - -x22c (ripp cmd_wr_data1 through ripp cmd wr_data3).
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 366 3) write the ripp cmd register with the command code and group tag for the command. 4) poll the ?cmd_busy? bit in the ripp command register and when cleared, check the status of the command. commands may be rejected when illegal actions are requested. an example of an illegal action is to start a lasr when one is already in progress. 4) if the command was a ?read_event? or ?read delay?, the returned data can now be read from the ripp command data register array located at addresses 0x240 ? 0x2be. 12.5.2 summary of ripp commands the following is a summary of all ripp commands that are currently supported. for the detailed command bit encoding info, refer to the ?registers? section. 1. add_group function add one new group to the device. note that this must be the first command to be issued to the group, if any other command is issued prior to this, it will be considered invalid and rejected. parameters group tag and vector of lids to be included in group pre-requisite require configuration of all link and group records as detailed in 12.4.3.1 and 12.4.3.2. restriction none. 2. delete_group function remove an existing group and all its links immediately. parameters group tag pre-requisite none. restriction none.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 367 3. restart_group function restart the specified group (gsm goes back to start-up state). parameters group tag pre-requisite if any group configuration info needs to be changed, pm must do so prior to issuing this command by writing to the ripp group configuration memory. restriction none 4. inhibit_group function set the internal group inhibiting status flag. once a group is considered inhibited, it will not go to operational state even if sufficient links exist in the group. if the group is already in operational state when the command is issued, the gsm will go to blocked state and thus block the tx data path. however the rx data path remains on. parameters group tag pre-requisite none. restriction none. 5. not_inhibit_group function clear the internal group inhibiting status. if the group is currently in blocked state and there are sufficient links in the group, the gsm will go to operational state. parameters group tag pre-requisite none. restriction none.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 368 6. start_lasr function start lasr procedure on one or more links. the links involved may either be new links or existing links with a failure/fault/inhibiting condition. tx_link_vec and rx_link_vec are 32-bit vectors with the same bit mapping as tx_phy_valid or rx_phy_valid respectively, the bits corresponding to the new links are set to ?1?. if the group configuration is symmetric, the tx_link_vec and rx_link_vec should be identical. parameters group tag and vector of lids to be included in lasr pre-requisite link records need to be properly initialized by pm prior to issue this command. also rdat/tima needs to be initialized properly to reflect the new links, if any. restriction this command will be rejected if there is currently an active lasr procedure. 7. delete_link function remove links from the group. the tx_link_vec and rx_link_vec fields indicate the links to be removed. if the group configuration is symmetric, the tx_link_vec and rx_link_vec should be identical. parameters group tag and vector of lids to be deleted pre-requisite none. restriction deletion of a trl link is a special case. a group will not be able to operate normally without both the tx trl and the rx trl. therefore, the trl link should not be deleted unless it is the last link in the direction. also, ima protocol requires there to be at least 1 link in both directions, therefore pm should not delete the last link left in either direction in cases other than a complete group removal.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 369 8. set_rx_phy_defect function indicate to ripp that the given link(s) have/have not physical defects (such as los/ais) which is not detectable internally. tx_link_vec and rx_link_vec indicate the links affected. parameters group tag and vector of lids to be included in group pre-requisite none. restriction none. 9. unusable_link function indicate to ripp that the given link(s) are unusable for certain reasons. tx_link_vec and rx_link_vec indicate the links affected. tx_cause and rx_cause indicates the reason for the link to be unusable. note it is possible to change the cause for the link to be unusable even after it enters the unusable state. parameters group tag and vector of lids to be made unusable and the cause to report why the link is unusable pre-requisite none. restriction it is required that pm must use one of the four defined causes (failed, fault, mis-connected, inhibited) if an unusable cause is to be reported to the far-end via the icp cell. 10. update_test_ptn function update the tx test pattern info to be sent in the outgoing icp cells for the group. this command also causes the scci field in the next outgoing icp cell to increase. parameters group tag and tx test pattern and test pattern lid pre-requisite none. restriction none.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 370 11. update_tx_trl function update the transmit timing information (tx trl and clock mode) to be sent in the outgoing icp cells. the trl is also used to control the tx idcc. this command also causes the scci field in the next outgoing icp cell to increase. parameters group tag and lid for new trl pre-requisite none. restriction it is up to the user to pick a valid trl to satisfy the requirement in the ima spec. at least, a trl that is currently configured to be in the group should be selected; otherwise the group will not be able to operate normally. 12. read_event function read and clear the latched event status of the specified group and all its' links. the result read from the internal context memory is stored in cmd_rd_data00 through cmd_rd_data1f. refer to the ?registers? section for further details. parameters group tag pre-requisite none. restriction this command will be rejected on deleted groups. 13. read_delay function read all the dcb write pointers and link defect status of all links in the specified group. the result is stored in cmd_rd_data00 through cmd_rd_data1f. refer to the ?registers? section for further details. parameters group tag pre-requisite none.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 371 restriction none. 14. adjust_delay function start an adjust_delay procedure on the specified group. the amount of delay to be removed/added is specified as part of parameters. parameters group tag and amount of delay in cells pre-requisite none. restriction this command will be rejected if there is currently another adjust_delay procedure in progress or if there is currently a group-wide procedure (group start-up or lasr) in progress. 12.5.3 adding a group in order to add a group, the group and link configuration should be performed. next, the add_group command should be issued. this command will initiate the group and link state machines. is starts the gsm arbitration and automatically starts a lasr procedure. the add_group command continues after the cmd_ack is returned. the completion of the command is generally indicated by an event that indicated either that the process timed-out or the group has become operational. if a timeout occurs, pm should take appropriate action and either restart the group with new parameters or add additional links to the group. the event that indicates that the add_group command has completed successfully is either the gtsm_int with the gtsm state = operational or gsm_int with the gsm state = operational. events that indicate that the add_group command has completed but was not successful are the following: ne_abort_int fe_abort_int group_timeout_int fe_timeout_int events that indicate that individual links are experiencing problems and did not become active are the following:
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 372 diff_delay_int invalid_icp_int rx_timeout_int tx_timeout_int in order to track the progress of the command, interrupts may be enabled for gsm state changes and for the lsm state changes for all of the links. this may result in a large number of events if the group includes a large number of links. note: if the trl link is not validated on the rx side, since the group does not have a valid trl, the group will not come up and will not report any events. if this happens, a restart_group command must be executed to recover. 12.5.4 deleting a group there are two methods of bringing a group down. to bring a group down and preserve data that has already been transmitted, it is recommended that the links be deleted first using the delete_link command. this will result in the gsm transitioning to the insufficient links state when the number of active links falls below the minimum required links. once the delete links is complete and all of the accumulated dcb data is played out, the delete_group command deletes the existing group. to determine if the deleted links have all of the dcb data played out, the tx_link_en and rx_link_en bits may be polled in the ripp link context records. once the delete_group command is executed, all links within the group will immediately stop transmitting ima frames, and all received cells queued in the dcb buffer will be dropped. if data preservation is not a concern, a group may be removed immediately by issuing the delete_group command. it is recommended that interrupts be disabled prior to the group deletion since the group deletion itself causes an interrupt to occur. if a read_event command is issued on a deleted group, the command will be rejected. if interrupts are not disabled, care must be taken to ensure proper servicing of the ripp interrupt fifo prior to reusing the group to avoid overrunning the ripp interrupt fifo (interrupt from group prior to deletion and interrupt from group after re-use both in fifo, and the fifo is sized to have a maximum of one event per group.) 12.5.5 restart group to restart a group or issue a local reset to a group, the restart_group command is used. upon a restart_group, the specified group?s gsm will immediately transition to the start-up state and try to renegotiate the ima parameters. this
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 373 command should be used after changing the m values, ima id, group symmetry, or oam value on a group. 12.5.6 inhibit group/not inhibit group to move a gsm into/out of the blocked state, the inhibit_group and not_inhibit_group commands may be used. these commands set a mode such that the current gsm state is not important. once set to the inhibit mode, the gsm will go to the blocked state instead of the operational state. the not_inhibit_group command must be executed to remove this setting. 12.5.7 adding a link or links to an existing group (start lasr) in order to add links to an existing group, the start_lasr command is used. prior to issuing this command, the link configuration should be performed as in 12.4.3.2. the start_lasr command will initiate the link addition and slow recovery procedure. the lasr procedure is paced by either (1) all of the indicated links? lsms transitioning to the appropriate states or (2) the programmed link timeouts in the presence of defective or slow links. the lasr procedure continues after the cmd_ack is returned. while a lasr procedure is in process, no other lasr procedure may be started on the same group. the completion of the command is generally indicated by an event that indicated either that the process timed-out or the links have become operational. if a timeout occurs, pm should take appropriate action and either restart the lasr procedure in the case that the handshaking was just slow or replace defective links. the event that indicates that the start_lasr command has completed successfully for symmetrical groups is the tx_active_int for all links involved. due to the group wide synchronization, this event should occur for all links simultaneously. for asymmetrical groups, the rx_active_int indicates the completion of the lasr for receive links. events that indicate that individual links are experiencing problems and did not become active are the following: diff_delay_int invalid_icp_int rx_timeout_int tx_timeout_int
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 374 if a timeout event occurs, another lasr procedure must be execute to continue attempting to bring links to the active state. in order to track the progress of the command interrupts may be enable the lsm state changes for all of the links. this may result in a large number of events if the group includes a large number of links. 12.5.8 reporting link defects in the icp cell lif, lods, and lcd defects are automatically detected and reported in the icp cell by the s/uni-ima-84. other physical layer defects such as los, oof, ais are not detected by the s/uni-ima-84. to enable reporting of these defects, the set_rx_defect command is provided to force the contents of the rdi field in the icp cell. 12.5.9 faulting/inhibiting links the s/uni-ima-84 reports defects to the upper layer s/w and allows the upper layer s/w declare fault conditions based upon defect information. in order to force a link into a fault or failure state, the unusable_link command is used. this link can operate on multiple links at a time. once executed, the lsm of the affected links are transitioned to the unusable state. if inhibiting the link without data loss is required, it is necessary to specify the cause as ?inhibited?. normally when inhibiting a link, the link has been active for a while. if a link is inhibited immediately after becoming active, data loss can occur. if the s/uni-ima-84 has not yet received icp cells from the link that indicates the link is active when the link is inhibited, data loss may occur. note that links currently experiencing defect conditions will still experience loss of data even when inhibiting. when links are faulted, the existing data within the dcb is still played out on the atm interface. 12.5.10 change trl to change the trl link, the update_trl command is used. the new trl is immediately used for scheduling the group and will be reported as the trl in the next icp cell. if ctc timing is used, the stuffing is not affected. if itc timing is used, the reference link is changed to the new trl. the first stuff on the new trl will occur on approximately the same frame as the stuff would have occurred when it was a non-reference link. after the first stuff on the new trl, the new trl will be stuffed every 2049 cells.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 375 12.5.11 deleting a link from a group a link can be deleted from a group by using the delete link command. on the transmit side, the link will stop accepting atm cells immediately and will transmit filler cells only. the links will be removed from the tx round-robin on the next frame boundary. on the receive side, the deleted link/links will transition to the deleted state to ensure that all transmitted data is received into the dcb buffer. once the fe tx state is detected as not active or the rx_link_deleted timeout occurs, the rx links stop writing data to the dcb buffers. the dcb buffers allowed to underrun (preserving any previously stored data) prior to being disabled and removed from the receive round-robin. the rx_enable bits and tx_enable bits in the ripp link context records should be monitored to determine when the links can be reassigned to a different group. 12.5.12 test pattern procedures the test pattern procedure consists of 2 parts, issuing the test pattern and checking the test pattern. to issue a test pattern, the update_tst_ptn command is used. this starts the transmission of the new test pattern. the s/uni-ima-84 will always loopback the test pattern indicated in the icp cell. since each link may experience different round trip delays, the checking of the test pattern is split between the user and the s/uni-ima84. the s/uni-ima-84 will compare test pattern received in the icp cell with the test pattern that was sent on every received icp cell. the s/uni-ima-84 stores the success or failure of this operation in the word 9 of the ripp group configuration register. the user is responsible for checking the results after a sufficient time has passed for a round trip delay on all links. note : if no icp cells are received for a particular lid, the rx_test_ptn_match field is never updated. 12.5.13 ima events all of ima events are reported via a group-based structure. ima events include link defects and link and group state machine changes. any enabled ima event will cause a ripp_intr. all ima events may be enabled for reporting at the group/link level as well as a globally. both the individual link/group enable as well as the global enable must be set to have an ima event cause an ripp_intr.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 376 as enabled ima events occur, a message is placed with the ripp_intr fifo. once a message is placed with the fifo, another message will not be generated until the read_event command is executed for the group. during this period of time, additional events can accumulate and will be reported with the read_event command when executed. the read_event command queries the links within the group and provides all of the link and group information in a single data structure. to ease the processing load, a map that shows which links are experiencing intr conditions is provided in page 0 of the returned status. page 1 contains the interrupt conditions and page 2 provides the status. the majority of the error/interrupt processing may be performed with the information provided by the read_event command. 12.5.14 end-to-end channel communication according to the ima spec, end-to-end channel is a proprietary communication channel via the corresponding field in the icp cells. the s/uni-ima-84 provides access to this facility through the following means: ? in the outgoing direction, the end-to-end channel may be updated by writing to the tx_end_channel field in the ripp group configuration record at any time. ? in the incoming direction, the end-to-end channel information may be accessed by reading the icp cell buffer memory. 12.6 diagnostic features 12.6.1 icp cell trace the s/uni-ima-84 can be configured to forward incoming icp cells to microprocessor, by setting the proper bits in the ripp group configuration memory. the content of the forwarded icp cell is stored in the icp cell buffer registers. the icp cell data exchange between ripp and the microprocessor is controlled via the use of a lock bit (which is located in the icp cell forwarding control register) and the pm_icp_avl interrupt. the data exchange protocol is as follows: 1. s/uni-ima-84 sees a new icp cell and starts polling the lock bit. 2. if the lock bit is current set, the cell is not forwarded.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 377 3. the icp cell data content is copied to the icp cell buffer registers. 4. the pm_icp_avl bit is set, this will cause an icp_cell_avl_int. 5. to read the icp cell, the lock bit must be set by writing ?1? to the icp_fwd_lock_req bit in the icp forwarding control register. once the lock is granted when the icp_fwd_lock_grant bit read back as ?1?. the lock bit must be set prior to clearing the interrupt, otherwise it is possible to have multiple interrupt generated. 6. the interrupt should be cleared by reading the icp cell forwarding status register. 7. the data may be readout from forwarding icp cell buffer registers. 8. the icp_fwd_lock_req should be cleared bit by writing to the register location. 12.6.2 sdram diagnostic access diagnostic access of the external sdram is provided to enable sdram initialization and testing. the access to the sdram is provided on a cell buffer granularity. each cell buffer is 64 bytes. by providing cell buffer burst access to the sdram, the sdram diagnostic accesses utilize the same burst access timing as is used when the s/uni-ima-84 is operating. prior to performing any diagnostic accesses to the sdram, the sdram interface must be placed in diagnostic mode. in diagnostic mode, all automatic accesses from the s/uni-ima-84 (except refresh) are disabled and all accesses are controlled via the microprocessor interface. to write to the sdram, first the image of the cell must be written into the sdram diag burst-write ram using the sdram diag burst ram indirect access. once the image of the cell has been written, a command to transfer the data into the external sdram should be issued using the sdram diag write cmd registers. the sdram diag write cmd registers specify the address of the cell buffer to be written in the external sdram. for a read operation, a read command is issued using the sdram diag read cmd registers. this command transfers data from the sdram into the internal cell buffer. when the command is complete as indicated by the rdbusy bit in the command register, the data may be read out of the cell buffer using the sdram diag burst ram indirect access.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 378 note that there is no crc protection for data in diagnostic mode. by providing both read command registers and write command registers, a back-to-back read/write access may be performed to the sdram. 12.7 ima performance parameters and failure alarms support a number of ima performance parameters and failure alarms are defined in the ima spec (section 12.2.2) as a standardized interface to ima unit management functions. the following text summarizes the support provided by s/uni-ima-84 to implement those functions. table 36 ima performance parameter support req. performance parameter s/uni-ima-84 support r-125 iv-ima o-20 oif-ima r-126 ses-ima ne rx ima defects will cause interrupts. r-127 ses-ima-fe rdi-ima defects will cause interrupts. r-128 uas-ima derived from ses-ima, no support. r-129 uas-ima-fe derived from ses-ima-fe, no support. r-130 tx-uus-ima s/uni-ima-84 provides read access to the tx lsm in ripp link context records. note after link start-up, it is up to pm to put the lsm into unusable state. r-131 rx-uus-ima s/uni-ima-84 provides read access to the rx lsm in link context records. note after link start-up, it is up to pm to put the lsm into unusable state. r-132 tx-uus-ima-fe s/uni-ima-84 may generate an interrupt once fe tx lsm enters unusable state. r-133 rx-uus-ima-fe s/uni-ima-84 may generate an interrupt once fe rx lsm enters unusable state.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 379 r-134 tx-fc failure condition is declared by pm, no support provided. r-135 rx-fc failure condition is declared by pm, no support provided. o-21 tx-fc-fe s/uni-ima-84 may generate an interrupt once fe tx lsm is in unusable state, pm may then read the fe lsm state in the ripp context memory to determine the case. o-22 rx-fc-fe s/uni-ima-84 may generate an interrupt once fe rx lsm is in unusable state, or a rdi-ima indication is sent by fe. o-23 tx-stuff-ima s/uni-ima-84 provides counter of inserted stuff events per link. o-24 rx-stuff-ima s/uni-ima-84 provide counter of received stuff events per link r-136 gr-uas-ima s/uni-ima-84 may generate an interrupt when a gtsm transition happens. r-137 gr-fc s/uni-ima-84 provides interrupt and read access to internal context for various error conditions. see table 37 for details. o-25 gr-fc-fe s/uni-ima-84 provides interrupt and read access to internal context for various error conditions. see table 37 for details. table 37 ima failure alarm support req. failure alarm s/uni-ima-84 support r-138 lif s/uni-ima-84 may generate an interrupt and latch the internal lif error status once a link enters or exits lif defect. r-139 lods s/uni-ima-84 may generate an interrupt and latch the internal lods error status once a link enters or
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 380 exits lods defect. r-140 rfi-ima s/uni-ima-84 may generate an interrupt and latch the internal rdi-ima status when rdi-ima condition is entered or exited on a tx link. it is up pm to declare the alarm condition. r-141 tx-mis-connected it is up to pm to detect mis-connectivity on tx links, possibly through the use of test patterns. fe may indicate that the link is mis-connected by moving the rx lsm to corresponding unusable state, in which case ripp will generate an interrupt and latch the error status. r-142 rx-mis-connected it is up to pm to detect mis-connectivity on rx links. one possible way is to utilize the rx_ima_id field in the group context. instead of letting ripp capture the rx_ima_id from incoming icp cells, pm can choose to initialize the group context with a expected rx_ima_id and set the rx_ima_id_valid field to ?1?. in this case the mis-connected rx links will likely to have a wrong ima id value and will not come up, which will eventually cause an interrupt. also pm may utilize the test pattern procedure for this purpose. o-28 tx-fault it is up to pm to declare fault conditions on tx links. to facilitate this, ripp provides read access to the ne/fe lsm and gsm states in the context memory. o-29 rx-fault it is up to pm to declare fault conditions on rx links. to facilitate this, ripp provides read access to the ne/fe lsm and gsm states in the context memory. r-143 tx-unusable-fe s/uni-ima-84 may generate an interrupt and latch the internal fe_tx_unusable error status, once fe tx lsm enters unusable state. r-144 rx-unusable-fe s/uni-ima-84 may generate an interrupt and latch the internal fe_rx_unusable error status, once fe
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 381 rx lsm enters unusable state. r-145 start-up-fe s/uni-ima-84 may generate an interrupt if a fe gsm state transition occurs. pm may then read the fe gsm state from the ripp context memory. r-146 config-aborted s/uni-ima-84 may generate an interrupt and latch the internal config-aborted error status, once it decides the fe parameters are unacceptable and the gsm should go to config-aborted state. r-147 config-aborted-fe s/uni-ima-84 may generate an interrupt and latch the internal config-aborted-fe error status, once it detects the fe gsm is in config-aborted state. r-148 insufficient-links s/uni-ima-84 may generate an interrupt if gsm state transition occurs. pm may then read the gsm state from the ripp context memory. r-149 insufficient-links-fe s/uni-ima-84 may generate an interrupt if a fe gsm state transition occurs. pm may then read the fe gsm state from the ripp context memory. r-150 blocked-fe s/uni-ima-84 may generate an interrupt if a fe gsm state transition occurs. pm may then read the fe gsm state from the ripp context memory. r-151 gr-timing-mis- match s/uni-ima-84 may generate an interrupt and latch the relevant error status, once it detects a mismatch between tx and rx clock modes.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 382 13 functional timing this section shows the functional relationship between inputs and outputs. no propagation delays are shown. 13.1 sbi drop bus interface timing figure 26 - sbi drop bus t1/e1 functional timing c1 v3 v3 v3 ds0#4. v5 ds0#9. refclk c1fp ddata[7:0] dpl dv5 ddp ??? ??? ??? ??? ??? ??? figure 26 illustrates the operation of the sbi drop bus, using a negative justification on the second to last v3 octet as an example. the justification is indicated by asserting dpl high during the v3 octet. the timing diagram also shows the location of one of the tributaries by asserting dv5 high during the v5 octet. figure 27 - sbi drop bus ds3 functional timing c1 h3 h3 h3 ds-3 #1 ds-3 #2 ds-3 #3 ds-3 #1 refclk c1fp ddata[7:0] dpl dv5 ddp ??? ??? ??? ??? ??? ???
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 383 figure 27 shows three ds-3 tributaries mapped onto the sbi bus. a negative justification is shown for ds-3 #2 during the h3 octet with dpl asserted high. a positive justification is shown for ds-3#1 during the first ds-3#1 octet after h3 (which has dpl asserted low). 13.2 sbi add bus interface timing the sbi add bus functional timing for the transfer of tributaries - whether t1/e1 or ds3 - is the same as for the sbi drop bus. the only difference is that the sbi add bus has a few additional signals. the ajust_req signal is used to by the temux-84 in sbi master timing mode to provide transmit timing to sbi link layer devices. the aactive signal is asserted whenever the s/uni-ima-84 is driving the sbi add bus and is used with the adetect signals of other link devices to detect and protect against sbi add bus conflicts. figure 28 - sbi add bus adjustment request functional timing c1 h3 h3 h3 ds-3 #1 ds-3 #2 ds-3 #3 ds-3 #1 refclk c1fp adata[7:0] apl av5 adp ajust_req aactive ??? ??? ??? ??? ??? ??? ??? ??? figure 28 illustrates the operation of the sbi add bus, using positive and negative justification requests as an example. (the responses to the justification requests would take effect during the next multi-frame.) the negative justification request occurs on the ds-3#3 tributary when ajust_req is asserted high during the h3 octet. the positive justification occurs on the ds-3#2 tributary when ajust_req is asserted high during the first ds-3#2 octet after the h3 octet. the aactive signal is shown for the case in which s/uni-ima-84 is driving ds-3#2 onto the sbi add bus.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 384 13.3 receive link input timing the timing relationship of the receive clock (rsclk[n]) and data (rsdata[n]) signals of an unchannelized link is shown in figure 29. the receive data is viewed as a contiguous serial stream. there is no concept of time-slots in an unchannelized link. each eight bits is grouped together into a byte with arbitrary alignment. the first bit received (b1 in figure 29) is deemed the most significant bit of an octet. the last bit received (b8) is deemed the least significant bit. bits that are to be processed by the s/uni-ima-84 are clocked in on the rising edge of rsclk[n]. bits that should be ignored (x in figure 29) are squelched by holding rsclk[n] quiescent. in figure 29, the quiescent period is shown to be a low level on rsclk[n]. a high level, effected by extending the high phase of the previous valid bit, is also acceptable. selection of bits for processing is arbitrary and is not subject to any byte alignment or frame boundary considerations. figure 29 - unchannelized receive link timing rsclk[n] rsdata[n] b1 b2 b3 b4 x b5 x x x b6 b7 b8 b1 x the timing relationship of the receive clock (rsclk[n]) and data (rsdata[n]) signals of a channelized t1 link is shown in figure 30. the receive data stream is a t1 frame with a single framing bit (f in figure 30) followed by octet bound time- slots 1 to 24. rsclk[n] is held quiescent during the framing bit. the rsdata[n] data bit (b1 of ts1) clocked in by the first rising edge of rsclk[n] after the framing bit is the most significant bit of time-slot 1. the rsdata[n] bit (b8 of ts24) clocked in by the last rising edge of rsclk[n] before the framing bit is the least significant bit of time-slot 24. in figure 30, the quiescent period is shown to be a low level on rsclk[n]. a high level, effected by extending the high phase of bit b8 of time-slot ts24, is equally acceptable. in channelized t1 mode, rsclk[n] can only be gapped during the framing bit. it must be active continuously at 1.544 mhz during all time-slot bits. time-slots can be ignored by setting the prov bit in the corresponding word of the receive channel provision ram in the rcas block to low.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 385 figure 30 - channelized t1 receive link timing rsclk[n] rsdata[n] b7b8 f b1b2b3b4b5b6b7b8b1b2b3 ts 24 ts 1 ts 2 the timing relationship of the receive clock (rsclk[n]) and data (rsdata[n]) signals of a channelized e1 link is shown in figure 31. the receive data stream is an e1 frame with a single framing byte (f1 to f8 in figure 31) followed by octet bound time-slots 1 to 31. rsclk[n] is held quiescent during the framing byte. the rsdata[n] data bit (b1 of ts1) clocked in by the first rising edge of rsclk[n] after the framing byte is the most significant bit of time-slot 1. the rsdata[n] bit (b8 of ts31) clocked in by the last rising edge of rsclk[n] before the framing byte is the least significant bit of time-slot 31. in figure 31, the quiescent period is shown to be a low level on rsclk[n]. a high level, effected by extending the high phase of bit b8 of time-slot ts31, is equally acceptable. in channelized e1 mode, rsclk[n] can only be gapped during the framing byte. it must be active continuously at 2.048 mhz during all time-slot bits. time-slots can be ignored by setting the prov bit in the corresponding word of the receive channel provision ram in the rcas block to low. figure 31 - channelized e1 receive link timing rsclk[n] rsdata[n] b6 b7 f1 f2 f3 f4 f5 f6 f7 f8 b1 b2 b3 ts 31 fas / nfas ts 1 b8 b4 b5 b6 b7 b8 b1 b2 b3 b4 ts 2 13.4 transmit link output timing the timing relationship of the transmit clock (tsclk[n]) and data (tsdata[n]) signals of a unchannelized link is shown in figure 32. the transmit data is viewed as a contiguous serial stream. there is no concept of time-slots in an unchannelized link. each eight bits is grouped together into a byte with arbitrary byte alignment. octet data is transmitted from most significant bit (b1 in figure 32) and ending with the least significant bit (b8 in figure 32). bits are updated on the falling edge of tsclk[n]. a transmit link may be stalled by holding the
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 386 corresponding tsclk[n] quiescent. in figure 32, bits b5 and b2 are shown to be stalled for one cycle while bit b6 is shown to be stalled for three cycles. in figure 32, the quiescent period is shown to be a low level on tsclk[n]. a high level, effected by extending the high phase of the previous valid bit, is also acceptable. gapping of tsclk[n] can occur arbitrarily without regard to either byte or frame boundaries. figure 32 - unchannelized transmit link timing tsclk[n] tsdata[n] b1 b2 b3 b4 b5 b6 b7 b8 b1 b2 the timing relationship of the transmit clock (tsclk[n]) and data (tsdata[n]) signals of a channelized t1 link is shown in figure 33. the transmit data stream is a t1 frame with a single framing bit (f in figure 33) followed by octet bound time-slots 1 to 24. tsclk[n] is held quiescent during the framing bit. the most significant bit of each time-slot is transmitted first (b1 in figure 33). the least significant bit of each time-slot is transmitted last (b8 in figure 33). the tsdata[n] bit (b8 of ts24) before the framing bit is the least significant bit of time-slot 24. in figure 33, the quiescent period is shown to be a low level on tsclk[n]. a high level, effected by extending the high phase of bit b8 of time-slot ts24, is equally acceptable. in channelized t1 mode, tsclk[n] can only be gapped during the framing bit. it must be active continuously at 1.544 mhz during all time-slot bits. time-slots that are not provisioned to belong to any channel (the prov bit in the corresponding word of the transmit channel provision ram in the tcas block set low) transmit the contents of the idle fill time-slot data register. figure 33 - channelized t1 transmit link timing w/ clock gapped low tsclk[n] tsdata[n] b7 b8 b1 b2 b3 b4 b5 b6 b7 b8 b1 b2 b3 ts 24 ts 1 ts 2 f
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 387 figure 34 - channelized t1 transmit link timing w/ clock gapped high tsclk[n] tsdata[n] b7 b8 b1 b2 b3 b4 b5 b6 b7 b8 b1 b2 b3 ts 24 ts 1 ts 2 f the timing relationship of the transmit clock (tsclk[n]) and data (tsdata[n]) signals of a channelized e1 link is shown in figure 35. the transmit data stream is an e1 frame with a single framing byte (fas/nfas in figure 35) followed by octet bound time-slots 1 to 31. tsclk[n] is held quiescent during the framing byte. the most significant bit of each time-slot is transmitted first (b1 in figure 35). the least significant bit of each time-slot is transmitted last (b8 in figure 35). the tsdata[n] bit (b8 of ts31) before the framing byte is the least significant bit of time-slot 31. in figure 35, the quiescent period is shown to be a low level on tsclk[n]. a high level, effected by extending the high phase of bit b8 of time-slot 31, is equally acceptable. in channelized e1 mode, tsclk[n] can only be gapped during the framing byte. it must be active continuously at 2.048 mhz during all time-slot bits. time-slots that are not provisioned to belong to any channel ? i.e., the prov bit in the corresponding word of the transmit channel provision ram in the tcas block is set low ? transmit the contents of the idle time-slot fill data register. figure 35 - channelized e1 transmit link timing w/ clock gapped low tsclk[n] tsdata[n] b6 b7 b1 b2 b3 ts 31 fas / nfas ts 1 b8 b4 b5 b6 b7 b8 b1 b2 b3 b4 ts 2 figure 36 - channelized e1 transmit link timing w/ clock gapped high tsclk[n] tsdata[n] b6 b7 b1 b2 b3 ts 31 fas / nfas ts 1 b8 b4 b5 b6 b7 b8 b1 b2 b3 b4 ts 2
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 388 alternatively, the ctsclk can be used instead of the tsclk[n] to lock the clocks of all the links together 13.5 any-phy/utopia l2 interfaces while the following diagrams present representative waveforms, they are not an attempt to unambiguously describe the interfaces. the pin description section is intended to present the detailed pin behavior and constraints on use. the following parameters apply to all any-phy/utopia interface figures: m = 7 for 8-bit mode, 15 for 16-bit mode k = is a function of 8/16 bit mode and number of prepends selected. 13.5.1 utopia l2 transmit slave interface figure 37 gives an example of the functional timing of the transmit interface when configured as a 31-port utopia l2 compliant transmit slave. the interface responds to the enabled addresses as defined by the register transmit cell available enable by asserting the tca corresponding to the addressed phy when it is capable of accepting a complete cell. as a result, the master selects one of the s/uni-ima-84?s phys by presenting the phy address again during the last cycle tenb is high. if the device had not been selected, tsoc, tdat[m:0], and tprty would have remained high-impedance. figure 37 illustrates that a cell transfer may be paused by deasserting tenb. the device is reselected by presenting the phy?s address the last cycle tenb is high to resume the transfer.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 389 figure 37 - utopia l2 transmit slave 1 tclk data k data k-1 data 0 data 1 ima-phy-x dev 1 ima-phy-x dev 2 data k-2 dev 3 data k-3 tclk tadr[4:0] tca tdat[m:0], tprty tenb tsop 13.5.2 any-phy transmit slave interface figure 38 gives an example of the functional timing of the transmit interface when configured as an 84-port any-phy compliant transmit slave. the any-phy master polls the ports in the s/uni-ima-84 and the s/uni-ima-84 device responds by driving tpa. if the s/uni-ima?s polled port is capable of accepting a complete cell, tpa is driven active otherwise the tpa is driven inactive. positive responses are recorded by the master and will eventually result in a data transfer. ports are selected for data transfers via an in-band address prepend in first word of the data transfer. polling continues independent of the data transfer state. data transfers are initiated with the assertion of tenb and tsx; they complete without pausing.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 390 figure 38 - any-phy transmit slave 2 tclk ima-adr phy 1 ima-adr phy 1 phy 0 phy 8 adr data 1 data 2 data k data 3 data k-1 data 1 ima-adr phy 7 tclk tadr[10:0] tcsb tpa tdat[m:0], tprty tenb tsx tsop 13.5.3 utopia l2 multi-phy receive slave interface figure 39 gives an example of the functional timing of the receive interface when configured as a 31-port utopia l2 compliant receive slave. the interface responds to addresses (as specified by the register receive cell available enable) by asserting the rca corresponding to the addressed phy when it is capable of providing a complete cell. as a result, the master selects one of the s/uni-ima-84?s phys by presenting the phy address again during the last cycle renb is high. had not the device been selected, rsoc, rdat[m:0], and rprty would have remained high-impedance. figure 39 illustrates that a cell transfer may be paused by deasserting renb. the device is reselected by presenting the phy?s address the last cycle renb is high to resume the transfer.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 391 figure 39 - utopia l2 multi-phy receive slave 1 2 3 4 5 6 7 8 9 10 1f phy- x 1f phy- y 1f phy- x 1f phy- z 1f phy- z 1f phy- x phy- y phy- x phy- z phy- z data k-3 data k-2 data k-1 data k data 0 data 1 data 2 data k- 1 rclk 1 rclk 1 rclk 1 rclk selection selection polling polling rclk radr[4:0] rca rdat[m:0], rprty renb rsoc 13.5.4 utopia l2 single-phy receive slave interface figure 40 gives an example of the functional timing of the receive interface when configured as a single port utopia l2 compliant slave. the interface responds to the address that matches the devid specified in the rxaps configuration register by asserting the rca when it is capable of providing a complete cell. as a result, the master selects the s/uni-ima-84 phys by presenting the phy address again during the last cycle renb is high. had not the device been selected, rsoc, rdat[m:0], and rprty would have remained high-impedance. figure 40 illustrates that a cell transfer may be paused by deasserting renb. the device is reselected by presenting the phy?s address the last cycle renb is high to resume the transfer. figure 40 - utopia l2 single-phy receive slave 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1f devi d 1f n+1 1f devi d 1f n+2 1f n+3 1f n+1 1f n 1f n+1 devid n+1 devi d d(n-3) d(n-2) d(n-1) d(n) d(0) d(1) d(2) d(n-1 ) d(n) d(0) d(1) d(2) d(3) pau s 1 rclk 1 rclk back 2 back cell back 2 back cell selection selection polling & reselection polling & reselection 16-bit utopia l2 single address slave rclk radr[4:0] rca rdat[m:0], rprty renb rsoc
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 392 13.5.5 any-phy receive slave interface figure 41 gives an example of the functional timing of the receive interface when configured as an any-phy compliant receive slave. the interface responds to the polling of address ?ima? (which matches the address defined by the receive any-phy/utopia config register) by asserting rpa when it is capable of delivering a complete cell. the any-phy master repolls addresses until it receives an asserted rpa. as a result, the master re-selects the same radr again during the last cycle renb is high to initiate a transfer. once transfer is initiated, renb must remain asserted until the last data is received. figure 41 - any-phy receive slave 1 2 3 4 5 6 7 8 9 10 1 f ima-a d 1 f phy- y 1 f ima- ad 1 f phy- z 1 f phy- z phy- a phy- z ima-ad r phy- y ima-ad r phy- z ima ad d data 0 data 1 2 rclk 2 rclk 2 rclk selection selection polling polling rclk radr[4:0] rcsb rpa rdat[m:0], rprty renb rsx rsop 13.6 sdram interface the following three diagrams depict the timing for signals destined for the pins of the sdram during the activate-read (with auto-precharge), activate-write (with auto-precharge), and auto-refresh command sequences and power-up and initialization sequence.. the cbcmd signal is not an actual signal; it merely represents the memory access command formed by the combination of the individual sdram control signals (e.g., cbcsb and cbrasb). also note that reads/writes of cell buffers are always done in bursts of eight words, with 4 bursts per cells; the first and third bursts involve the even banks and the second and fourth bursts involve the odd banks in the sdram.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 393 figure 42 - sdram read timing 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 act 0 desel/no p rd 0 desel/no p act desel/no p rd1 desel/nop even ban k odd ban k even ban k even ro w even co odd ro w odd col even ro w pre a odd ro w pre a d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d1 0 d1 1 d1 2 d1 3 d1 4 d1 5 trcd trcd trcd sdram read mode timing act2 desel/nop rd2 d1 6 even row odd row even col prea sysclk cbcmd cbcsb cbrasb cbcasb cbweb cbdqm cbbs[1:0] cba[11, 9:0] cba[10] cbdq[15:0]
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 394 figure 43 - sdram write timing 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 act 0 desel/nop wr 0 desel/nop act1 desel/nop wr1 desel/nop even ban k odd ban k even ban k even ro w even co odd ro w odd col even ro w pre a odd ro w pre a d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d1 0 d11 d1 2 d1 3 d1 4 d1 5 even ro w odd ro w trcd trcd sdram write mode timing act2 desel/nop d1 6 even row even row even col sysclk cbcmd cbcsb cbrasb cbcasb cbweb cbdqm cbbs[1:0] cba[11, 9:0] cba[10] cbdq[31:0] cba[11]
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 395 figure 44 - sdram refresh 1 2 3 4 5 6 7 8 9 10 11 12 ref a desel/nop act desel/nop 00 400h trc sdram refresh mode timing sysclk cbcmd cbcsb cbrasb cbcasb cbweb cbdqm cbbs[1:0] cba[11:0] cbdq[15:0]
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 396 figure 45 - power up and initialization sequence 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 nop pr e nop re f nop re f nop m r 00 400h 03 3 trc (9cyc) trp (3cyc) sdram initialization sequence (78 cyc) refa & trc (9 cyc) sequence must be repeated 8 times, prior to mrs cbri performs first arbitration on cycle following mrs sysclk vcc bucb_cben cbcmd cbcsb cbrasb cbcasb cbweb cbdqm cbbs[1:0] cba[11:0] cbdq[15:0]
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 397 14 absolute maximum ratings maximum ratings are the worst case limits that the device can withstand without sustaining permanent damage. they are not indicative of normal mode operation conditions. table 38 absolute maximum ratings ambient temperature under bias -40c to +85c storage temperature -40c to +125c 1.8v supply voltage -0.3v to +3.6v 3.3v supply voltage -0.3v to +6.0v voltage on any pin(except 5v compatible) -0.3v to v vddo +0.3v voltage on any pin( 5v compatible) -0.3v to 5.5v static discharge voltage 1000 v latch-up current 100 ma dc input current 20 ma lead temperature +230c absolute maximum junction temperature +150c
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 398 15 d. c. characteristics t a = -40c to +85c, v dd = vdd typical 8% (typical conditions: t c = 25c, v vddi = 1.8v, v vddo = 3.3v, v avddq = 3.3v) table 39 d.c. characteristics
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 399 symbol parameter min typ max units conditions v vddi power supply 1.656 1.8 1.944 volts v vddo power supply 3.03 3.3 3.56 volts v vddq power supply 3.03 3.3 3.56 volts v il input low voltage 0 0.8 volts guaranteed input low voltage. v ih1 input high voltage for inputs: tsclk[31:0], tck, rsclk[31:0], rclk, tclk, rstb, sysclk, ctsclk, refclk, wrb, rdb, ddata[7:0], ddp, dc1fp, dv5, adetect, ac1fp, ajust_req 2.2 volts guaranteed input high voltage. v ih2 input high voltage for all other inputs and bidirects 2.0 volts guaranteed input high voltage. v ol output or bi- directional low voltage tbd 0.4 volts guaranteed output low voltage at vdd=3.03v and i ol =maximum rated for pad. v oh output or bi- directional high voltage 2.4 tbd volts guaranteed output high voltage at vdd=3.03v and i oh =maximum rated current for pad. v t+ reset input high voltage 2.0 volts applies to rstb and trstb only. v t- reset input low voltage 0.8 volts applies to rstb and trstb only.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 400 v th reset input hysteresis voltage tbd volts applies to rstb and trstb only. i ilpu input low current 10 200 a v il = gnd. notes 1 and 3. i ihpu input high current -10 0 +10 a v ih = v dd . notes 1 and 3. i il input low current -10 0 +10 a v il = gnd. notes 2 and 3. i ih input high current -10 0 +10 a v ih = v dd . notes 2 and 3. c in input capacitance 5 pf t a =25c, f = 1 mhz c out output capacitance 5pft a =25c, f = 1 mhz c io bi-directional capacitance 5pf t a =25c, f = 1 mhz i ddop operating current tbd ma v dd = max, outputs unloaded notes on d.c. characteristics: 1) input pin or bi-directional pin with internal pull-up resistor. 2) input pin or bi-directional pin without internal pull-up resistor. 3) negative currents flow into the device (sinking), positive currents flow out of the device (sourcing).
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 401 16 a.c. timing characteristics (tc = -40c to +85c, vdd = 3.3 v 8%) notes on input timing: 1. when a set-up time is specified between an input and a clock, the set-up time is measured from the 50% point of the input to the 50% point of the clock. 2. when a hold time is specified between a clock and an input, the hold time is measured from the 50% point of the clock to the 50% point of the input. notes on output timing: 1. output timing is measured between the 50% point of the clock to the 50% point of the output. 16.1 microprocessor interface timing characteristics table 40 microprocessor interface read access symbol parameter min max units ts ar address to valid read set-up time 5 ns th ar address to valid read hold time 5 ns ts alr address to latch set-up time 5 ns th alr address to latch hold time 5 ns tv l valid latch pulse width 20 ns ts lr latch to read set-up 0 ns th lr latch to read hold 5 ns tp rd valid read to valid data propagation delay 30 ns tz rd valid read negated to output tristate 20 ns tz inth valid read negated to output tristate 50 ns
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 402 figure 46 - microprocessor interface read timing intb tz inth (csb+rdb) valid data d[15:0] tp rd tz rd ts ar th ar valid address a [10:1] a le ts alr tv l ts lr th alr th lr notes on microprocessor interface read timing: 1. maximum output propagation delays are measured with a 100 pf load on the microprocessor interface data bus (d[15:0]). 2. a valid read cycle is defined as a logical or of the csb and the rdb signals. 3. in non-multiplexed address/data bus architectures, ale should be held high so that parameters tsalr, thalr, tvl, and tslr are not applicable. 4. parameter thar is not applicable if address latching is used.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 403 table 41 microprocessor interface write access symbol parameter min max units ts aw address to valid write set-up time 5ns ts dw data to valid write set-up time 10 ns ts alw address to latch set-up time 5 ns th alw address to latch hold time 5 ns tv l valid latch pulse width 20 ns ts lw latch to write set-up 0 ns th lw latch to write hold 5 ns th dw data to valid write hold time 5 ns th aw address to valid write hold time 5ns tv wr valid write pulse width 20 ns
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 404 figure 47 - microprocessor interface write timing th dw valid data d[15:0] tv wr ts aw th aw ts dw (csb+wrb) a [10:1] valid address a le tv l ts alw ts lw th alw th lw notes on microprocessor interface write timing: 1. a valid write cycle is defined as a logical or of the csb and the wrb signals. 2. in non-multiplexed address/data bus architectures, ale should be held high so that parameters ts alw , ts alw , tv l , ts lw and th lw are not applicable. 3. parameter th aw is not applicable if address latching is used. table 42 rtsb timing symbol description min max units tvrstb rstb pulse width 100 ns
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 405 figure 48 - rstb timing 16.2 synchronous i/o timing figure 49 - synchronous i/o timing tp tzb tz th ts clk input output table 43 sysclk and refclk timing symbol description min max units f sysclk frequency, sysclk 20 55 mhz d sysclk duty cycle, sysclk 40 60 % f refclk frequency, refclk (see note 1) 19.44 ? 50 ppm 19.44 +50 ppm mhz f refclk frequency, refclk (see note 2) 52 mhz d sysclk duty cycle, refclk 40 60 % notes: 1. applicable only when operating with the sbi interface.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 406 2. applicable only when operating with the clk/data interface. table 44 cell buffer sdram interface symbol description min max units ts input set-up time to sysclk 2.5 th input hold time to sysclk 0 tp sysclk high to output valid 1 10 ns tz sysclk high to output high-impedance 1 10 ns tzb sysclk high to output driven 1 ns maximum output propagation delays are measured with a 20pf load on the outputs. minimum output propagation delays are measured with a 0 pf load on the outputs. table 45 any-phy/utopia transmit interface symbol description min max units f clk tclk frequency 52 d clk tclk duty cycle 40 60 % ts input set-up time to tclk (except tcsb) 4 ns ts input set-up time to tclk ( tcsb only) 6 ns th input hold time to tclk 0 ns tp tclk high to output valid 1 12 ns tz tclk high to output high-impedance 1 12 ns tzb tclk high to output driven 1 ns maximum output propagation delays are measured with an 50pf load on the outputs. minimum output propagation delays are measured with a 0 pf load on the outputs.
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 407 table 46 any-phy/utopia receive interface symbol description min max units f clk rclk frequency 52 mhz d clk rclk duty cycle 40 60 % ts input set-up time to rclk (except rcsb) 4ns ts input set-up time to rclk (rcsb) 6 ns th input hold time to rclk 0 ns tp rclk high to output valid 1 12 ns tz rclk high to output high-impedance 1 12 ns tzb rclk high to output driven 0 ns maximum output propagation delays are measured with an 50pf load on the outputs. minimum output propagation delays are measured with a 0 pf load on the outputs. table 47 serial link input symbol description min max units rsclk[31:0] frequency (see note 1) 1.542 1.546 mhz rsclk[31:0] frequency (see note 2) 2.046 2.05 mhz rsclk[7:0] (see note 3) 8 mhz rsclk[31:8] (see note 3) 2.304 mhz rsclk[31:0] duty cycle 40 60 % ts rd rsdata[31:0] set-up time 5 ns th rd rsdata[31:0] hold time 5 ns
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 408 notes: 1. applicable only to channelized t1 links and measured between framing bits. 2. applicable only to channelized e1 links and measured between framing bytes. 3. applicable only to unchannelized links of any format and measured between any two rclk rising edges table 48 serial link output symbol description min max units tsclk[31:0] frequency (see note 3) 1.542 1.546 mhz tsclk[31:0] frequency (see note 4) 2.046 2.05 mhz tsclk[7:0] frequency (see note 5) 8 mhz tsclk[31:8] frequency (see note 5) 2.304 mhz tsclk[31:0] duty cycle 40 60 % t p td tsclk[31:0] low to tsdata[31:0] valid. see note 1. 227ns notes on output timing: 1. maximum output propagation delays are measured with a 50 pf 2. minimum output propagation delays are measured with a 0 pf 3. applicable only to channelized t1 links and measured between framing bits. 4. applicable only to channelized e1 links and measured between framing bytes. 5. applicable only to unchannelized links of any format and measured between any two tclk rising edges
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 409 16.3 sbi timing table 49 sbi frame pulse timing symbol description min max units ts c1fp ac1fp and dc1fp set-up time to refclk 4ns th c1fp ac1fp and dc1fp hold time to refclk 0ns figure 50 - sbi frame pulse timing refclk c1fp ts c1fp th c1fp table 50 sbi drop bus timing symbol description min max units ts sbidrop all sbi drop bus inputs set-up time to refclk 4ns th sbidrop all sbi drop bus inputs hold time to refclk 0ns
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 410 figure 51 - sbi drop bus timing refclk ts sbidrop th sbidrop ddata[7:0] ddp, dpl dv5 table 51 sbi add bus symbol description min max units ts sbiadd ajust_req set-up time to refclk 4 ns th sbiadd ajust_req hold time to refclk 0 ns t p aactive refclk to aactive valid 0 15 ns t p sbiadd refclk to all sbi add bus outputs (except aactive) valid 020ns t z sbiadd refclk to all sbi add bus outputs (except aactive) tristate 015ns t p outen adetect low to all sbi add bus outputs (except aactive) valid 012ns t z outen adetect high to all sbi add bus outputs (except aactive) tristate 012ns
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 411 figure 52 - sbi add bus timing refclk adata[7:0] adp, apl, av5 ajust_req ts siadd th abiadd tp sbiadd tz sbiadd adata[7:0] adp, apl, av5 aactive tp aactive figure 53 - sbi add bus collision avoidance timing adetect[n] tp outen tz outen adata[7:0] adp, apl, av5
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 412 16.4 jtag timing table 52 jtag port interface symbol description min max units tck frequency 1 mhz tck duty cycle 40 60 % ts tms tms set-up time to tck 50 ns th tms tms hold time to tck 50 ns ts tdi tdi set-up time to tck 50 ns th tdi tdi hold time to tck 50 ns tp tdo tck low to tdo valid 2 50 ns tv trstb trstb pulse width 100 ns
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 413 figure 54 - jtag port interface timing ts tms th tms tms tck ts tdi th tdi tdi tp tdo tdo tck trstb tv trstb
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 414 17 ordering and thermal information table 53 ordering and thermal information part no. description PM7341 416 plastic ball grid array (pbga) table 54 thermal information - theta ja vs. airflow forced air (linear feet per minute) theta ja @ specified power conv 100 200 300 400 500 dense board 28.5 25.7 24.0 22.9 22.4 22.2 jedec board 21.2 19.5 18.3 17.5 16.9 16.4
preliminary inverse multiplexing over atm PM7341 s/uni-ima-84 datasheet pmc-2000223 issue 4 inverse multiplexing over atm proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 415 18 mechanical information figure 55 - 416 pin pbga ?27x27 mm body ? (p suffix) e1 e d d1 0.20 (2x) a b a1 ball cor- ner 45 o chamfer 4 places available marking area 0.20 (2x) top view bbb c aaa c c 30 typ +/- 1% == a 2 a a 1 c seating plane side view bottom view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af a1 ball corner b e e j i "d" dia. 3 places px py package type : 416 plastic ball grid array - pbga body size : 27 x 27 x 2.28 mm (4 layer) dim. a (2 layer) a 1 a 2 dd 1 ee 1 ij b (4 layer) d px py aaa bbb min. 2.07 0.40 1.12 0.50 -- nom. 2.28 0.50 1.17 27.00 24.00 27.00 24.00 1.00 1.00 0.63 0.61 1.0 0 -- max. 2.49 0.60 1.22 0.70 0.15 0.35 e - - 1.00 (2 layer) 0.36 1.82 2.03 2.22 a (4 layer) - - - - - - c c 0.40 0.30 0.67 0.55 25.00 25.10 24.90 24.90 25.00 25.10 - - - - bsc bsc bsc bsc notes: 1) all dimensions in millimeter. 2) dimension aaa denotes coplanarity. 3) dimension bbb denotes parallel.

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